Array Substrate Via Design for Aperture Ratio

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-resolution liquid crystal displays face issues with reduced aperture ratio due to vias connecting source/drain electrodes and pixel electrodes, and increased frame width and impedance from ITO Bridge structures in the peripheral-driving circuit.

Innovation Solution

A manufacturing method for an array substrate that directly connects the first and second metal layers via vias, eliminating the need for ITO Bridge and reducing frame width, while enhancing the aperture ratio and electrical characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If vias are used to connect source/drain electrodes and pixel electrode, then electrical connection is achieved, but aperture ratio is reduced

Engineering Contradiction:
Improveelectrical connectionVSAvoidaperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the via structure from the pixel electrode connection method. Instead of using vias to connect the source/drain electrode to the pixel electrode, the invention directly connects them through a planar contact structure, eliminating the need for vertical via holes and thereby increasing the aperture ratio while maintaining electrical connection reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from a vertical connection approach (via holes penetrating through layers) to a horizontal/planar connection approach. The source/drain electrode directly contacts the pixel electrode in the same plane or through a planar interface, changing the connection dimension from vertical to lateral, which eliminates the aperture loss caused by via holes

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If ITO Bridge structure is used to connect first metal layer and second metal layer in peripheral-driving circuit, then electrical connection is achieved, but frame width is increased

Engineering Contradiction:
Improveelectrical connectionVSAvoidframe width
Core Design Contradiction:
ReliabilityVSLength of stationary object

Solution Approach 1:

The patent removes the ITO Bridge structure from the peripheral-driving circuit connection method. Instead of using ITO bridges to connect the first metal layer (scanning line) and second metal layer (data line), the invention uses a direct metal-to-metal contact or a planar conductor structure, eliminating the need for ITO bridges and thereby reducing the frame width while maintaining electrical connection

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the material and structural parameters of the connection bridge. By replacing ITO (indium tin oxide) with a different conductor material or structure that has different dimensional characteristics, the frame width is reduced. The connection structure is optimized to have smaller lateral dimensions while maintaining adequate electrical conductivity

Inventive Principle:
Principle #35Parameter changes

3Reliability

If ITO Bridge structure is used in peripheral-driving circuit, then electrical connection is achieved, but bridge impedance is increased

Engineering Contradiction:
Improveelectrical connectionVSAvoidbridge impedance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent changes the material parameters of the connection structure. By replacing ITO with a different conductor material that has lower resistivity, the bridge impedance is reduced. The material selection is optimized to provide adequate electrical conductivity with lower resistance, thereby reducing the harmful impedance effect on the peripheral-driving circuit signals

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10192909B2Array substrate structure and manufacturing method of array substrate
Publication Date: 2019.01.29 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
  • US10192909B2 patent drawing
  • US10192909B2 patent drawing
  • US10192909B2 patent drawing

AI summary

The present invention involves an array substrate structure and a manufacturing method of an array substrate. The manufacturing method of an array substrate, which comprises: Step 1, a substrate is provided, a first metal layer is manufactured on the substrate, and the first metal layer is patterned with a first photo-mask, to manufacture a gate electrode. Step 2, a gate insulating layer is manufactured on the substrate; an active layer is manufactured with a second photo-mask. Step 3, a first via is formed in the gate insulating layer corresponding to the first metal layer with a third photo-mask. Step 4, a second metal layer is manufactured on the gate insulating layer, the second metal layer is patterned with a fourth photo-mask, to manufacture source/drain electrodes, and a second via is formed on where corresponding to the active layer, the first metal layer and the second metal layer are connected at the first via. Step 5, a pixel electrode is manufactured with a fifth photo-mask, the pixel electrode and the source/drain electrodes are directly connected at the second via; the second metal layer is covered and protected by the pixel electrode. The present invention also provides a corresponding array substrate structure. The invention can enhance the aperture ratio of the pixel at high-resolution and the display effect and quality of the liquid crystal display and improve the electrical characteristics of the panel.