Array Substrate Via Formation Eliminating Drain Undercut

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The existing methods for manufacturing array substrates face a problem of undercut occurring under the drain due to the dry etching process, which causes the second transparent conductive layer to break at the undercut position.

Innovation Solution

A method that includes forming a pattern with a main via penetrating through the gate insulating layer and passivation layer, and a main-via extension portion under the drain, followed by removing the protruding portion of the drain using a wet etching process to form a final via, ensuring the connection electrode connects the drain to the pixel electrode without breaking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a dry etching process is used to form the main via penetrating through the gate insulating layer and passivation layer, then the via can be formed effectively, but undercut occurs under the drain causing the second transparent conductive layer to break

Engineering Contradiction:
Improvevia formation precisionVSAvoidstructural integrity of transparent conductive layer
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent forms a main-via extension portion that protrudes below the drain before the drain is removed. This preliminary structural preparation allows the via to be properly formed and positioned, and then the protruding portion is removed in a subsequent step to eliminate the undercut issue while maintaining via formation effectiveness

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts or removes the protruding portion of the main-via extension portion that extends below the drain after the via is formed. This removal eliminates the harmful undercut structure that would cause the transparent conductive layer to break, while preserving the functional via structure

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If the main via is formed to penetrate through the gate insulating layer and passivation layer, then electrical connection is achieved, but the protruding portion of the drain causes undercut and structural failure

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidvia structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The via structure is segmented into two parts: the main via that provides electrical connection and the main-via extension portion that protrudes below the drain. This segmentation allows the via to fulfill its electrical connection function while the extension portion can be selectively removed to eliminate undercut without affecting the via's primary function

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively eliminates the undercut issue without adding extra process steps, resulting in improved performance and higher yield of the array substrates.

Implementation Method 1

removing the protruding portion of the drain using a wet etching process to form a final via

Methodology Applied
Scientific EffectWet etching:

Data Source

PatentEP3327763B1Method for manufacturing array substrate, array substrate, and display device
Publication Date: 2022.03.02 BOE TECHNOLOGY GROUP CO LTD
  • EP3327763B1 patent drawingFigure 1~4
  • EP3327763B1 patent drawingFigure 5~7
  • EP3327763B1 patent drawingFigure 8

AI summary

The present invention provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing an array substrate comprises: forming a pattern comprising a pixel electrode and a pattern comprising a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming a pattern comprising an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a pattern comprising a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a pattern comprising a final via; and forming a pattern comprising a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.