Array Substrate Via Flange for Reliable Common Electrode Connection

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Solution Overview

Problem

The existing array substrates face poor electrical connections between the common electrode line and the common electrode due to breaches formed on the side walls of vias, resulting from the large thicknesses of the passivation and etch stop layers during the formation of the connection portion.

Innovation Solution

The array substrate design incorporates a main via with a flange extending away from its center, featuring an upper and lower main connection portion, where the lower end of the upper connection portion is connected to the flange, and the upper end is connected to the common electrode, ensuring a continuous and uniform metal layer for reliable electrical connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the passivation layer and etch stop layer are made with large thicknesses to ensure proper insulation and structural integrity, then the electrical connection between the common electrode line and the common electrode deteriorates due to breaches formed on the side wall of the via during connection portion formation

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidvia side wall integrity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent introduces a flange structure that extends horizontally from the via, creating a new dimensional solution. The flange provides a lateral connection path that bypasses the vertical via side wall problem, allowing the connection portion to form reliably without breaching the thick passivation and etch stop layers. This dimensional transition from vertical to lateral connection resolves the contradiction between layer thickness and connection integrity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The connection structure is segmented into distinct components: the via, the flange, and the connection portion. This segmentation allows each component to be optimized independently - the via maintains vertical electrical connection, the flange provides lateral support and connection surface, and the connection portion forms the actual electrical bond. This segmentation enables reliable connection despite the presence of thick insulating layers.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If a simple via structure is used to connect the common electrode line and the common electrode, then the manufacturing process remains simple, but breaches are likely to be formed on the via side wall resulting in poor electrical connection

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidelectrical connection quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

By adding the flange that extends horizontally from the via, the patent creates a multi-dimensional connection structure. This flange structure provides additional surface area for the connection portion to form, ensuring reliable electrical connection without significantly complicating the manufacturing process. The flange can be formed using standard photolithography and etching techniques.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The flange acts as an intermediary structure between the via and the connection portion. It provides a stable lateral surface that facilitates the formation of the connection portion, mediating the connection between the common electrode line and the common electrode. This intermediary structure ensures reliable connection while maintaining manufacturing simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9966389B2Array substrate and manufacturing method thereof and display device
Publication Date: 2018.05.08 BOE TECHNOLOGY GROUP CO LTD
  • US9966389B2 patent drawing
  • US9966389B2 patent drawing
  • US9966389B2 patent drawing

AI summary

This invention provides an array substrate, a manufacturing method thereof and a display device, the array substrate comprises a common electrode line, a thin film transistor and a common electrode, the common electrode line is provided below an active layer of the thin film transistor, and is provided with a main via thereabove, the common electrode is electrically connected to the common electrode line through a main connection portion in the main via, the main connection portion comprises an upper main connection portion and a lower main connection portion, the lower main connection portion comprises a main body and a flange provided on the main body and extending towards a direction away from a center of the main via, a lower end of the upper main connection portion is connected to the flange, an upper end of the upper main connection portion is connected to the common electrode.