Array Substrate Via Structure for Blocking Gas Penetration
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Solution Overview
Problem
Existing array substrates face issues with gas penetration through via structures, affecting the electrical stability of thin film transistors due to the absence of adequate passivation, which compromises the reliability of electrical connections between pixel electrodes and drain electrodes.
Innovation Solution
The array substrate design includes a passivation layer covering drain electrodes and a via structure that ensures electrical connection through multiple vias, with an annular or overlapping via projection design to enhance contact area and block gas penetration, using materials like silicon nitride or silicon oxide for insulating layers and transparent metal oxides for electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a via structure is used to connect pixel electrode to drain electrode, then electrical connection is achieved, but gas can penetrate through the via affecting TFT stability
Solution Approach 1:
The patent implements a nested via structure where a third via is positioned inside the projection area of a second via. The second via connects the pixel electrode to the drain electrode, while the third via extends deeper to connect to the active layer. This nested configuration allows the via structure to serve dual purposes: maintaining electrical connectivity while the overlapping projection area creates a blocked pathway that prevents gas penetration to the TFT, thus resolving the contradiction between achieving electrical connection and preventing gas harm.
Solution Approach 2:
The patent introduces an intermediary via structure (the third via) that mediates between the pixel electrode connection and the TFT protection needs. The third via acts as a barrier or intermediary element that blocks gas pathways while the second via maintains electrical connection. This intermediary structure prevents direct gas access to the TFT active layer, resolving the contradiction by adding a mediating element that serves both connectivity and protection functions.
2Reliability
If multiple vias are used to enhance electrical connection, then contact area increases, but device structure becomes more complex
Solution Approach 1:
The patent merges the functions of multiple vias by positioning the third via within the projection area of the second via. Instead of creating separate, independent via structures that would increase complexity, the patent combines them into a nested configuration where the third via is integrated within the second via's projection area. This merging approach enhances electrical contact reliability through increased contact area while minimizing structural complexity by using a compact nested design rather than multiple dispersed via structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves the electrical stability and reliability of thin film transistors by blocking gas penetration, enhancing the electrical contact between pixel electrodes and drain electrodes, thereby improving the overall performance and stability of the array substrate.
Implementation Method 1
a common electrode layer is formed on a lower surface of the array substrate in a sputtering process
Data Source
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AI summary
An array substrate includes a base substrate including a plurality of pixel regions arranged in an array; a plurality of thin film transistors distributed within respective ones of the plurality of pixel regions, each of the thin film transistors including an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode including a first portion located in a second via; a passivation layer located on the source electrodes and the drain electrodes, the passivation layer covering the first portions of the drain electrodes; and a plurality of pixel electrodes distributed within respective ones of the plurality of pixel regions and located on the passivation layer, each of the pixel electrodes being electrically connected to a respective one of the drain electrodes through a respective third via that extends through the passivation layer.