Array Substrate Via Structure for Reliable GOA Electrode Connection
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Solution Overview
Problem
The existing array substrates in display panels face issues with connecting electrodes prone to disconnection in vias, leading to poor operation of the gate driver on array (GOA) circuits and subsequent poor display effects due to inefficient etching processes that result in defects and columnar compound formation.
Innovation Solution
The method involves forming an array substrate with a specific structure of insulating layers and vias, using different etching gases to create a stepped structure in the vias, ensuring a strong lap joint between the connecting electrode and the first electrode, reducing disconnection likelihood by optimizing the angle and thickness of the insulating layers and the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching treatment is performed on multiple insulating layers, then the manufacturing process is simple, but the etching efficiency is low and columnar compounds form causing via defects
Solution Approach 1:
The etching process is segmented into multiple sequential treatments, each targeting specific insulating layers with appropriate etching gases. The first etching treatment uses a first etching gas for the first and second insulating layers, while the second etching treatment uses a second etching gas for the third insulating layer. This segmentation improves etching efficiency and prevents columnar compound formation without significantly complicating the overall manufacturing process.
2Ease of manufacture
If the via size is uniform throughout all insulating layers, then the manufacturing process is simple, but the connecting electrode cannot form a strong lap joint with the first electrode
Solution Approach 1:
The via structure is designed with asymmetric dimensions across different insulating layers. The via in the first insulating layer has a first size, the via in the second insulating layer has a second size different from the first, and the via in the third insulating layer has a third size different from both. This asymmetric design enables the connecting electrode to form a strong lap joint with the first electrode, improving electrical connection reliability while maintaining manufacturing feasibility through sequential etching treatments.
3Loss of time
If the insulating layers are etched simultaneously, then the process time is short, but the etching precision is poor resulting in via defects
Solution Approach 1:
The etching process is performed in preliminary sequential stages rather than simultaneously. The first etching treatment prepares the via through the first and second insulating layers, followed by the second etching treatment to complete the via through the third insulating layer. This preliminary action approach ensures high via formation precision by allowing optimization of etching parameters for each layer, while the sequential nature minimizes total process time compared to multiple separate etching cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical connection between TFTs in the GOA circuit, improving the display effect by reducing disconnection issues and maintaining a strong lap joint, thus ensuring a better performance of the display panel.
Implementation Method 1
performing a first etching treatment and a second etching treatment on the at least two insulating layers
Data Source
AI summary
Provided is an array substrate. The array substrate includes: a substrate, and a first electrode, a connecting electrode, and at least two insulating layers arranged on the substrate, wherein the first electrode is disposed on a side, proximal to the first electrode, of the at least two insulating layers, and the connecting electrode is disposed on a side, facing away from the substrate, of the at least two insulating layers; and at least two communicated vias are arranged in the at least two insulating layers, a size of a first via, most proximal to the substrate, in the at least two vias is less than sizes of other vias, and the connecting electrode is lapped with the first electrode via the at least two vias.