Array Substrate Via Hole Design for High PPI AMOLED Displays
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Solution Overview
Problem
The existing oxide top gate technology for AMOLED displays requires a large region for punching to connect the light shielding layer with the active layer, which hinders the achievement of high pixels per inch (PPI) due to the need for multiple via holes and precise alignment, making it difficult to implement high pixel resolution.
Innovation Solution
An array substrate design that includes a via hole with a first part penetrating through the interlayer dielectric and buffer layers to expose the light shielding layer and a second part penetrating through the interlayer dielectric to expose the active layer, allowing the source drain layer to be electrically connected with both layers through a single via hole, reducing the required connection area and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large region for punching is used to connect the light shielding layer with the active layer, then reliable electrical connection is achieved, but the pixel resolution (PPI) deteriorates due to increased area occupation
Solution Approach 1:
The via hole is divided into two distinct parts: a first part that penetrates through the interlayer dielectric layer and buffer layer to expose the light shielding layer, and a second part that penetrates through the interlayer dielectric layer to expose the active layer. This segmentation allows each part to serve a specific connection function while sharing a common opening, thereby reducing the total area required for connection and enabling higher pixel resolution without compromising electrical connection reliability.
2Reliability
If multiple via holes are used to connect the light shielding layer with the active layer, then adequate electrical connection is established, but the device complexity increases
Solution Approach 1:
The patent merges the functions of multiple via holes into a single via hole structure. The first part of the via hole establishes electrical connection between the source drain layer and the light shielding layer, while the second part establishes connection between the source drain layer and the active layer. This merging reduces the number of separate via holes from two or more to one, thereby simplifying the device structure and reducing manufacturing complexity while maintaining adequate electrical connection reliability.
3Manufacturing precision
If precise alignment is required for multiple via holes, then connection accuracy is improved, but the manufacturing process complexity increases
Solution Approach 1:
The via hole structure is designed with predetermined geometric relationships between its first and second parts. The opening at the top surface of the interlayer dielectric layer is formed first, followed by selective etching to create the first part extending to the light shielding layer and the second part extending to the active layer. This preliminary action approach establishes the connection pathway before final layer deposition, reducing the need for complex post-alignment procedures and simplifying the manufacturing process while maintaining connection accuracy.
Data Source
AI summary
The present disclosure provides an array substrate, a display panel, a display device and a manufacturing method, for solving the problems in the prior art that the array substrate is larger in number of circuits, the area needed for punching is larger, and the high pixel resolution cannot be achieved easily. The array substrate comprises: an interlayer dielectric layer located at the side of the active layer distant from the buffer layer, the interlayer dielectric layer being provided with a via hole, the via hole comprising a first part and a second part, the orthographic projection of the first part on the base substrate being in contact with the orthographic projection of the second part on the base substrate, the first part of the via hole penetrating through the interlayer dielectric layer and the buffer layer and exposing part of the shading layer, and the second part penetrating through the interlayer dielectric layer and exposing at least part of the active layer; and a source/drain layer located at the side of the interlayer dielectric layer distant from the active layer.