Array Substrate Via Hole Design for Bubble Prevention
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Solution Overview
Problem
Existing color filter on array (COA) products face issues with bubble generation due to overlapping via holes and differences in etching rates between the color resist layer and passivation layer, leading to incomplete gas release and reduced transmittance or aperture ratio.
Innovation Solution
An array substrate design featuring a passivation layer via hole that penetrates through both passivation layers and the color resist layer, with inclined surfaces and vents to facilitate gas escape from the color resist layer, ensuring complete gas release before cell formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the via hole of the color resist layer is enlarged to avoid overlapping with the via hole of the passivation layer, then bubble generation is reduced, but the aperture ratio is reduced
Solution Approach 1:
The via hole structure is segmented into multiple functional zones: an upper via hole portion, a middle color resist layer portion with vents, and a lower passivation layer portion. This segmentation allows the color resist layer portion to be smaller (maintaining aperture ratio) while the upper portion provides sufficient gas release capability (preventing bubbles).
Solution Approach 2:
Vents are formed in the color resist layer portion of the via hole before cell formation. This preliminary action creates predetermined gas release channels that allow trapped gas to escape during subsequent processing steps, preventing bubble generation without requiring an enlarged overall via hole structure.
2Loss of time
If the color resist layer is opened first and then the passivation layer via hole is formed, then etching time is reduced, but the via hole is vertical and not conducive to ITO electrode layer covering
Solution Approach 1:
The color resist layer portion is formed with vents and an inclined surface configuration before the passivation layer via hole is completed. This preliminary action creates a tapered structure that facilitates subsequent ITO electrode layer deposition and covering, while also reducing the overall etching time by establishing the basic structure early in the process.
Solution Approach 2:
The via hole structure incorporates an inclined surface in the color resist layer portion, creating a tapered or curved configuration rather than a purely vertical shape. This curvature facilitates ITO electrode layer covering by providing a gradual transition surface, while the overall structure remains efficient for gas release.
3Reliability
If a hole is opened in the color resist layer to release gas in advance, then gas release is enabled, but the etching depth is insufficient due to lower etching rate of color resist layer compared to passivation layer
Solution Approach 1:
The via hole is segmented such that the color resist layer portion has a specific depth optimized for gas release, while the overall via hole extends through multiple layers. Vents are formed at strategic positions within the color resist layer portion to provide sufficient gas release capability without requiring excessive etching depth into the color resist layer.
Solution Approach 2:
Vents are strategically positioned within the color resist layer portion of the via hole to create localized gas release channels. This local quality enhancement ensures effective gas release at critical positions without requiring the entire via hole to be excessively deep, optimizing the balance between gas release capability and etching depth.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces the risk of bubble occurrence in liquid crystal panels by ensuring complete gas release from the color resist layer, maintaining aperture ratio, and preventing ITO electrode breakage.
Implementation Method 1
a passivation layer via hole is provided above the source/drain layer, the passivation layer via hole penetrates the second passivation layer, the color resist layer, and the first passivation layer, and extends to a surface of the source/drain layer, and a side of the passivation layer via hole exposes the color resist layer to allow gas in the color resist layer to escape
Data Source
AI summary
The present invention provides an array substrate and a method of fabricating the same, wherein the array substrate includes a base substrate, a gate layer, a gate insulating layer, a source/drain layer, a first passivation layer, a color resist layer and a second passivation layer, wherein a passivation layer via hole is provided above the source/drain layer, and gas in the color resist layer releases from a surface of the color resist layer on a side of the passivation layer via hole. The invention realizes the purpose of completely discharging the gas in the color resist layer before a cell formation process.