Array Substrate Via Hole Design for Low Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
All-in-cell touch panels suffer from high contact resistance between conductive layers, leading to issues such as being stuck and poor touch performance during the touch period.
Innovation Solution
The array substrate design includes a first conductive layer with higher electrical conductivity than a second conductive layer, with via holes and planarization layers to facilitate direct contact between the touch electrode and the first conductive layer, reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a second conductive layer is added to protect the first conductive layer, then the structural integrity is improved, but the contact resistance increases
Solution Approach 1:
The patent introduces a planarization layer as an intermediary between the second conductive layer and the touch electrode. This planarization layer contains contact holes that expose the first conductive layer, allowing the touch electrode to directly contact the high-conductivity first conductive layer while the second conductive layer remains intact for structural protection. This mediator structure resolves the contradiction by enabling direct electrical contact through the planarization layer without compromising the protective function of the second conductive layer.
Solution Approach 2:
The patent segments the contact path into distinct functional zones: the second conductive layer provides structural protection in non-contact areas, while the planarization layer with contact holes creates localized exposure points where the first conductive layer directly contacts the touch electrode. This segmentation allows different layers to perform their optimized functions - protection where needed and conduction where required - thereby reducing overall contact resistance while maintaining structural integrity.
2Ease of manufacture
If the touch electrode contacts the second conductive layer, then the manufacturing process is simplified, but the electrical conductivity decreases
Solution Approach 1:
The patent applies local quality by creating contact holes in the planarization layer at specific locations where electrical contact is needed. The planarization layer maintains its planar structure for ease of manufacturing, but locally exposes the first conductive layer through contact holes to provide high electrical conductivity at the touch electrode interface. This local modification allows the majority of the structure to remain simple and manufacturable while achieving superior electrical performance at critical contact points.
3Reliability
If via holes are created to expose the first conductive layer, then the contact resistance is reduced, but the manufacturing complexity increases
Solution Approach 1:
The patent merges the formation of contact holes in the planarization layer with the existing via hole formation process for the second conductive layer. By integrating these hole-forming operations into a single manufacturing sequence, the patent reduces the overall manufacturing complexity despite adding the planarization layer. The combined process creates both the protective via holes through the second conductive layer and the contact holes through the planarization layer simultaneously, minimizing additional process steps.
Data Source
AI summary
An array substrate, a method for fabricating the same, and a display device are provided. The array substrate includes: a base substrate; touch electrode wiring including a first conductive layer and a second conductive layer, where the first conductive layer is between the base substrate and the second conductive layer, the second conductive layer includes at least one first via hole to expose the first conductive layer, and the first conductive layer has a higher electrical conductivity than that of the second conductive layer; a planarization layer on the second conductive layer, where the planarization layer includes at least one first touch electrode contact hole; and touch electrode on the planarization layer, where the touch electrode is connected with the first conductive layer through the first touch electrode contact hole and the first via hole.