Array Substrate Via Hole Filling for Display Flatness
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Solution Overview
Problem
The uneven diffusion of the polyimide (PI) orientation layer due to the height difference between via holes and the surrounding transparent electrically conductive layer in TFT-LCD manufacturing leads to image quality issues like PI dark Mura and uneven brightness in the peripheral regions of display panels.
Innovation Solution
A method is introduced to fill via holes with a filler, such as photoresist, during the formation of the second transparent electrically conductive layer, ensuring the top surface of the via holes is in the same horizontal plane as the surrounding conductive layer, thereby eliminating the height difference and ensuring even PI diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via holes are formed in the display panel during TFT-LCD manufacturing, then electrical connections are established between layers, but the height difference between via hole top surface and surrounding transparent electrically conductive layer causes uneven diffusion of the PI orientation layer
Solution Approach 1:
The via holes are filled with filler material (such as photoresist or insulating material) during the formation process of the transparent electrically conductive layer, before the PI orientation layer is applied. This preliminary filling action ensures that the surface is already flattened when the PI layer is coated, preventing uneven diffusion and eliminating the need for subsequent surface correction steps.
2Manufacturing precision
If the top surface of via holes is filled to be in the same horizontal plane as the surrounding conductive layer, then uneven PI diffusion is prevented, but additional manufacturing steps are required
Solution Approach 1:
The filling process of the via holes is merged with the formation process of the transparent electrically conductive layer. The filler material is applied and patterned simultaneously with the conductive layer deposition and patterning steps, so that both the via hole filling and the conductive layer formation are completed in one integrated process sequence, avoiding the need for separate filling steps.
3Reliability
If via holes are formed in peripheral regions, then electrical connections are provided, but PI dark Mura and brightness traces occur due to rugged surface
Solution Approach 1:
The filling operation is applied selectively to via holes located in the peripheral regions of the display panel where PI dark Mura and brightness traces are most problematic. The filler material is deposited and patterned to specifically address the surface irregularities in these critical areas, ensuring local surface flatness improvement where it is most needed for display quality.
Data Source
AI summary
An array substrate and a manufacturing method thereof, a display panel and a display device are disclosed. The method for manufacturing an array substrate includes: forming a first via hole for connecting a second transparent electrically conductive layer and a gate line layer, a second via hole for connecting a first transparent electrically conductive layer and the second transparent electrically conductive layer, and a third via hole for connecting the second transparent electrically conductive layer and a source/drain electrode layer on a base substrate through patterning process; performing a filling process on the first via hole, the second via hole and the third via hole during a pattern of second transparent electrically conductive layer is being formed, such that each of the three via holes has a top surface which is flush with the second transparent electrically conductive layer surrounding the respective via holes.