Array Substrate Via Hole Overlap for Electrode Adhesion

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Solution Overview

Problem

Conventional liquid crystal display panels face issues with the pixel electrode and drain electrode of the TFT being easily detached at their connections, leading to a low defect-free rate of the array substrate.

Innovation Solution

The array substrate design includes a first and second insulation layer with conductive patterns connected through via holes, where the second conductive pattern is in contact with the first insulation layer, enhancing adhesion and preventing peeling off at connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the pixel electrode is connected to the drain electrode through a via hole in conventional array substrate, then the electrical connection is established, but the adhesion between the pixel electrode and drain electrode is poor causing easy detachment

Engineering Contradiction:
Improveconnection reliabilityVSAvoidadhesion strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent transitions from a single via hole connection to a dual via hole configuration, adding another dimensional aspect to the connection structure. The first via hole provides mechanical anchoring by penetrating through the pixel electrode to the drain electrode, while the second via hole establishes electrical connection, creating a multi-dimensional connection solution that simultaneously addresses both adhesion and conductivity requirements.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces an insulation layer as an intermediary element between the pixel electrode and drain electrode. This insulation layer, positioned between the two conductive elements, prevents direct contact that would cause short circuits while the via holes penetrate through it to establish controlled connection points, mediating both the electrical and mechanical interaction between the electrodes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If a single via hole is used to connect pixel electrode and drain electrode, then the structure is simple, but the defect-free rate is low due to detachment issues

Engineering Contradiction:
Improvestructure complexityVSAvoiddefect-free rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the single via hole connection into two separate via holes with distinct functions. The first via hole is dedicated to mechanical anchoring and adhesion, while the second via hole handles electrical connection. This segmentation allows each via hole to be optimized for its specific purpose, improving overall connection reliability without creating a overly complex structure.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dual via hole configuration creates a multi-functional connection system where the via holes serve multiple purposes: the first via hole provides mechanical support and adhesion, the second via hole ensures electrical connectivity, and together they form a redundant connection system that improves defect-free rate while maintaining reasonable structural complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10678106B2Array substrate, liquid crystal display panel and display device
Publication Date: 2020.06.09 BOE TECHNOLOGY GROUP CO LTD
  • US10678106B2 patent drawing
  • US10678106B2 patent drawing
  • US10678106B2 patent drawing

AI summary

An array substrate, a liquid crystal display panel and a display device are disclosed. The array substrate includes a first insulation layer disposed on a base substrate, a first conductive pattern disposed on the first insulation layer, a second insulation layer disposed on the first conductive pattern, a second conductive pattern disposed on the second insulation layer. The second conductive pattern is connected to the first conductive pattern through a second via hole penetrating the second insulation layer. The array substrate further includes a first via hole exposing the first insulation layer and penetrating the first conductive pattern. An orthogonal projection of the first via hole on the base substrate and an orthogonal projection of the second via hole on the base substrate at least partially overlap with each other, the second conductive pattern is connected to the first insulation layer through the first via hole.