Array Substrate Via-Hole Formation Using Variable Photoresist Thickness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing processes for AMOLED array substrates face challenges in forming via-holes for switching and driving TFTs, as they either damage the active layer or require additional patterning steps, leading to inefficiencies in etching and increased complexity.
Innovation Solution
A method involving a single patterning process for forming via-holes using a photoresist layer with varying thicknesses and a slit or gray tone mask to control etching, allowing for partial etching in the switching TFT region and complete etching in the driving TFT region, thereby reducing damage and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single patterning process is used to form via-holes for both switching TFT and driving TFT, then the manufacturing process is simplified and productivity is improved, but the active layer pattern may be damaged due to excessive etching in the switching TFT region
Solution Approach 1:
The photoresist layer is formed with different thicknesses in different regions: a first thickness in the switching TFT region and a second thickness (greater than the first) in the driving TFT region. This local variation in thickness allows the etching process to be automatically controlled - the thicker photoresist in the driving TFT region protects against over-etching while the thinner photoresist in the switching TFT region allows complete etching through, thus preventing damage to the active layer pattern while maintaining manufacturing efficiency
Solution Approach 2:
The photoresist layer is prepared in advance with spatially varying thickness before the etching process begins. This preliminary configuration of different thicknesses ensures that during the subsequent single etching process, each region receives the appropriate level of protection without requiring separate patterning steps, thereby resolving the contradiction between process simplification and damage prevention
2Manufacturing precision
If the etching process is continued to completely remove the gate insulation layer in the driving TFT region, then the via-hole is properly formed, but the active layer pattern in the switching TFT region is damaged
Solution Approach 1:
By forming the photoresist layer with a greater thickness in the driving TFT region compared to the switching TFT region, the patent creates a local quality difference that controls the etching depth in each region. The thicker photoresist in the driving TFT region allows the etching process to continue until the gate insulation layer is completely removed and the via-hole is properly formed, while the thinner photoresist in the switching TFT region limits the etching depth to prevent damage to the active layer pattern
Solution Approach 2:
The photoresist layer acts as an intermediary protective layer with spatially varying thickness. It mediates the etching process by providing differential protection: sufficient protection in the switching TFT region to prevent active layer damage, and controlled removal in the driving TFT region to allow complete via-hole formation. This intermediary layer resolves the contradiction between achieving precise via-hole formation and preventing collateral damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the time and damage to the active layer during etching and simplifies the manufacturing process by using a single patterning step, ensuring accurate formation of via-holes without damaging the active layer or requiring additional patterning processes.
Implementation Method 1
photoresist is applied on the etching stopping layer 5, and a single patterning process is performed to form a photoresist removed region at regions above the via-holes A11, A12, B1
Implementation Method 2
a dry etching process is performed until the gate insulation layer and the etching stopping layer in a region corresponding to the via-hole B1 are completely etched off
Data Source
AI summary
Embodiments of the invention provide an array substrate and a method of manufacturing the same. The method comprises: forming a gate electrode pattern, a gate insulation layer, an active layer pattern and an etching stopping layer on a substrate; forming a photoresist layer on the etching stopping layer; performing a single patterning process on the photoresist layer, such that photoresist in the first region is partially etched off, photoresist in the second region is completely etched off, and photoresist in the third region is completely remained; and performing a single etching process, such that residual photoresist in the first region and a portion of the etching stopping layer in the first region are etched off, and at the same time, a portion of the etching stopping layer and a portion of the gate insulation layer in the second region are etched off.