Array Substrate Via Interconnects for Copper Swelling Prevention
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Solution Overview
Problem
The high temperature process in manufacturing array substrates using the Through Glass Via (TGV) technique causes copper to swell, leading to poor disconnection between signal lines and integrated circuit chip traces, resulting in film layer rupture and electrical disconnection.
Innovation Solution
An array substrate design featuring a base substrate with connection vias filled with a first conductive material, an inorganic insulating layer with penetrating vias, and a second conductive layer on the side of the first and second vias, ensuring electrical connection between the conductive material and lead-out lines, thereby avoiding high temperature processes that cause copper swelling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature process is used in TGV manufacturing, then copper filling is achieved, but copper swelling occurs causing film layer rupture and electrical disconnection
Solution Approach 1:
The patent replaces the traditional high temperature process with a low temperature electroplating process to fill the TGVs with conductive material. This parameter change in processing temperature prevents copper swelling while achieving reliable electrical connections, directly resolving the contradiction between connection reliability and manufacturing precision
Solution Approach 2:
The patent substitutes the thermal field (high temperature process) with an electrochemical field (electroplating process) to fill the vias. This replacement of the physical mechanism eliminates the thermal expansion and swelling issues while maintaining effective conductive material deposition, solving the contradiction between reliable connection and dimensional control
2Device complexity
If TGV technique is used to connect electronic components, then three-dimensional integration is achieved, but copper swelling causes poor disconnection between signal lines and chip traces
Solution Approach 1:
The patent changes the processing temperature parameter from high to low, using electroplating instead of thermal processing. This prevents copper swelling that would otherwise cause poor disconnection between signal lines and chip traces, while maintaining the three-dimensional integration structure
Solution Approach 2:
The patent introduces an intermediary protective layer structure that prevents direct contact between the copper-filled TGVs and the overlying film layers during high temperature processes. This intermediary layer acts as a barrier to prevent copper swelling from rupturing the film layers and causing disconnection, while still allowing electrical connection through the via
Data Source
AI summary
The disclosure relates to an array substrate and a manufacturing method therefor, a display panel, and a display device. The array substrate comprises a base substrate, and a lead-out line and an inorganic insulating layer which are located on one side of the base substrate; the base substrate is provided with a plurality of connection vias penetrating the base substrate and filled with a first conductive material; the inorganic insulating layer is provided with a first via and a second via, the first via penetrating to the first conductive material, and the second via penetrating to the lead-out line; a second conductive layer is disposed on the side, away from the base substrate, of the first via, the second via and the inorganic insulating layer, such that the first conductive material and the lead-out line are electrically connected through the second conductive layer.