Array Substrate Via Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
Improving the aperture ratio of liquid crystal display panels is essential for enhancing pixel density, as existing designs face challenges with parasitic capacitance and power consumption due to close proximity of signal lines and common electrodes.
Innovation Solution
The array substrate design includes a signal line positioned proximate to the base substrate, with a first via hole exposing parts of the signal line and a connection electrode, allowing for increased spacing between the signal line and common electrode, thereby reducing parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the signal line is positioned close to the common electrode to improve pixel density, then the aperture ratio increases, but parasitic capacitance increases and power consumption increases
Solution Approach 1:
The patent introduces a via hole structure that extends vertically through insulating layers, transforming the horizontal proximity problem into a vertical connection solution. This allows the signal line to be positioned close to the common electrode in the horizontal plane while maintaining electrical isolation through the via hole architecture, thereby increasing aperture ratio without proportionally increasing parasitic capacitance.
Solution Approach 2:
The patent introduces an intermediate connection structure consisting of the via hole and connection electrode that mediates between the signal line and common electrode. This intermediary architecture allows for optimized spacing and reduced parasitic capacitance while maintaining the desired aperture ratio, effectively decoupling the direct horizontal proximity that causes excessive capacitance.
2Area of moving object
If the signal line is positioned close to the common electrode to enhance pixel density, then the aperture ratio improves, but parasitic capacitance increases
Solution Approach 1:
The via hole structure extends the connection path into the vertical dimension, allowing horizontal proximity for high aperture ratio while using vertical spacing and insulating layers to control parasitic capacitance. This dimensional transformation enables independent optimization of aperture ratio and capacitance.
Solution Approach 2:
The connection electrode and via hole structure serve as an intermediary that controls the electric field distribution between the signal line and common electrode. This intermediary architecture reduces parasitic capacitance by optimizing the spacing and configuration while maintaining the desired aperture ratio.
3Loss of energy
If the spacing between signal line and common electrode is increased to reduce parasitic capacitance, then power consumption decreases, but pixel density decreases
Solution Approach 1:
The patent resolves the spacing dilemma by moving the connection path to the vertical dimension via via holes. This allows horizontal spacing to be minimized for high pixel density while vertical insulation and via hole configuration control parasitic capacitance and power consumption, achieving both goals simultaneously.
Solution Approach 2:
The patent segments the connection path into distinct vertical layers separated by insulating layers. This segmentation allows the signal line and common electrode to be positioned close horizontally for high pixel density while the insulating layers and via hole structure control parasitic capacitance, enabling independent optimization of both parameters.
Data Source
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Figure 7A~7C
AI summary
An array substrate. The array substrate comprises a base substrate, a signal line, a first insulating layer, an active layer and a first via hole, wherein the signal line is located on the base substrate; the first insulating layer is located on the side of the signal line away from the base substrate; the active layer is located on the side of the first insulating layer away from the base substrate, and comprises a first portion, a second portion, and a channel structure, which is located between the first portion and the second portion; the first via hole penetrates at least the first insulating layer, and exposes at least part of the signal line; the first portion is configured to connect to the signal line by means of the first via hole; the materials of the second portion and the first portion are the same as the material of the channel structure; and the electrical conductivity of the channel structure is different from that of the first portion, and is different from that of the second portion.