Array Substrate Via Layout for Virtual Reality Pixel Aperture
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Solution Overview
Problem
Virtual reality liquid crystal display products suffer from a screen window effect when close to the user's eyes due to insufficient pixel aperture ratio, which is primarily attributed to the connection method between the metal oxide semiconductor layer and the data line.
Innovation Solution
The array substrate design includes a metal oxide semiconductor layer with a first part connected to the data line through a via hole, forming a stripe shape with an included angle greater than 0 degrees and less than or equal to 90 degrees, and a second part overlapping with the gate line's orthographic projection but not the data line's, enhancing the pixel aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the metal oxide semiconductor layer is connected to the data line through a conventional source electrode structure, then the electrical connection is reliable, but the pixel aperture ratio is reduced
Solution Approach 1:
The patent extracts and removes the conventional source electrode structure from the pixel region. By eliminating this intermediate component, the semiconductor layer is directly connected to the data line, thereby removing the obstacle that reduced the pixel aperture ratio while maintaining electrical connection through the via hole structure
Solution Approach 2:
The patent changes the connection approach from a planar source electrode structure to a vertical via hole connection. The semiconductor layer extends into the via hole to establish electrical connection with the data line, utilizing the vertical dimension to achieve both reliable electrical connection and maximized pixel aperture area
2Illumination intensity
If the pixel aperture ratio is increased by removing the source electrode structure, then light transmittance is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent merges the semiconductor layer formation process with the via hole structure creation. The semiconductor layer is formed to extend into the via hole in the same fabrication sequence, combining what would otherwise be separate manufacturing steps into a unified process, thereby reducing overall manufacturing complexity despite the innovative structure
Solution Approach 2:
The via hole structure is prepared in advance before the semiconductor layer is deposited. This preliminary action allows the semiconductor layer to be formed with the appropriate shape and extension into the via hole in a single subsequent step, simplifying the manufacturing process compared to forming the connection structure after layer deposition
Data Source
AI summary
An array substrate and a display panel, the array substrate includes: a base substrate; a gate line and a data line on the base substrate, the gate line intersect the data line to define a pixel region; a metal oxide thin film transistor is arranged in the pixel region, the metal oxide thin film transistor includes a metal oxide semiconductor layer; the metal oxide semiconductor layer includes a first part and a second part; the first part and the data line are connected through a first via hole; the first part is in a stripe shape; a first included angle is between extension directions of the first part and the data line; an orthographic projection of the second part overlap with an orthographic projection of the gate line on the base substrate and do not overlap with an orthographic projection of the data line on the base substrate.