Array Substrate Electrode Layout for Lower Via-Step Open-Circuit Risk
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The array substrate in display devices is prone to open circuits due to a high climbing height of the lap electrode, leading to poor electrical connection between the GOA circuit and gate lines, which affects the display effect.
Innovation Solution
The array substrate design includes a first and second electrode with vias, where the orthographic projection of the first electrode covers the region between the vias, reducing the height difference and climbing height of the lap electrode, thereby improving electrical connection by stacking the first and second insulating layers between and around the vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lap electrode has a large height difference to connect different layers, then the electrical connection between GOA circuit and gate lines is achieved, but the probability of open circuits increases
Solution Approach 1:
The patent divides the lap electrode into multiple segments (first lap electrode segment and second lap electrode segment) positioned at different heights. The first segment is at a first height from the substrate, while the second segment is at a second height that is lower than the first height. This segmentation reduces the overall height difference that needs to be bridged, thereby lowering the probability of open circuits while maintaining electrical connection between the GOA circuit and gate lines.
Solution Approach 2:
The patent introduces a vertical dimension strategy by positioning electrode segments at different heights above the substrate. Instead of using a single tall lap electrode spanning the entire height difference, the solution creates multiple shorter vertical steps. The first lap electrode segment extends from the gate line toward the first via hole, and the second lap electrode segment extends from the second via hole toward the common electrode, with each segment occupying a different vertical zone. This dimensional approach distributes the electrical connection path across multiple height levels, reducing stress and open circuit risk.
2Reliability
If the first electrode and second electrode are positioned to overlap, then the height difference is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by making the overlap between the first electrode and second electrode partial rather than complete. The orthographic projection of the first electrode on the substrate is at least partially overlapped with an orthographic projection of the second electrode on the substrate, but the first electrode's projection also covers a region between at least one first via and at least one second via. This localized partial overlap strategy reduces the cumulative alignment error across the entire electrode area, making manufacturing more feasible while still achieving the height difference reduction benefit in the overlapping region.
3Reliability
If multiple vias are used to connect the lap electrode to different electrodes, then the electrical connection is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple via holes (first via holes and second via holes) into a integrated via structure that serves dual purposes. The first via holes penetrate through the first insulating layer to electrically connect the first electrode to the first lap electrode segment, while the second via holes penetrate through the second insulating layer to electrically connect the second electrode to the second lap electrode segment. By positioning these vias in a coordinated manner with the segmented lap electrode, the patent creates a unified electrical connection system that improves reliability without proportionally increasing complexity.
Data Source
AI summary
Provided is an array substrate, including: a substrate; a first insulating layer and a second insulating layer that are successively stacked; a first electrode disposed on a side, proximal to the substrate, of the first insulating layer; a second electrode disposed between the first insulating layer and the second insulating layer; and a lap electrode disposed on a side, distal from the substrate, of the second insulating layer. The array substrate includes a plurality of first vias and a plurality of second vias. The lap electrode is electrically connected to the first electrode and is electrically connected to the second electrode. An orthographic projection of the first electrode on the substrate is overlapped with an orthographic projection of the second electrode on the substrate, and covers a region between at least one of the first vias and at least one of the second vias.