Array Substrate Wire Groove Geometry for Resistance Uniformity

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Solution Overview

Problem

In display panels, the varying lengths of lead wires connected to different pins on a chip result in significant resistance differences, leading to display abnormalities such as non-uniform brightness and reliability issues due to unequal resistance across the panel.

Innovation Solution

The array substrate incorporates first and second lead wires arranged in wire grooves with specific geometries, where first lead wires cover the bottom and sidewalls of grooves to increase their effective width and reduce resistance, while second lead wires are placed on recesses and protrusions to increase their effective length, ensuring equal resistance across the panel.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If lead wires are arranged with uniform material, thickness, and width, then manufacturing is simplified, but resistance varies significantly due to different lengths causing display abnormalities

Engineering Contradiction:
Improvelead wire arrangement simplicityVSAvoiddisplay uniformity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by creating different groove structures for different lead wire positions. First wire grooves have smooth bottoms for lead wires connected to end pins, while second wire grooves have recesses and protrusions for lead wires connected to central pins. This allows each lead wire to have its effective width adjusted locally according to its specific position and length, compensating for resistance differences without changing the overall manufacturing process complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the geometric parameters of the wire grooves to control lead wire dimensions. By modifying the groove cross-sectional shapes (smooth vs. recess-protrusion structures), the effective width of lead wires is adjusted, which directly changes their resistance characteristics. This allows uniform resistance across different lead wire lengths while maintaining consistent material and thickness.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If lead wire lengths are made uniform, then resistance is equalized, but chip size constraints make this difficult to achieve

Engineering Contradiction:
Improveresistance uniformityVSAvoidlead wire arrangement complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent solves the length uniformity problem by transitioning from controlling lead wire length to controlling lead wire width through groove geometry. Instead of making all lead wires the same length (which is impossible due to chip positioning), the invention adjusts the effective width of lead wires in different positions using differently shaped grooves, thereby equalizing resistance through a dimensional parameter change rather than length control.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If lead wire resistance is reduced, then signal transmission improves, but lead wire width must be increased consuming more space

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidperipheral circuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent applies local quality by providing different groove structures only where needed. First wire grooves (for end pins) have smooth bottoms with moderate width, while second wire grooves (for central pins) have recesses and protrusions that increase effective width only in specific segments. This localized modification reduces resistance where necessary without uniformly increasing the area occupied by all lead wires.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10541257B2Array substrate, display panel and display device
Publication Date: 2020.01.21 BOE TECHNOLOGY GROUP CO LTD
  • US10541257B2 patent drawing

AI summary

The disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a peripheral circuit area in which a plurality of first wire grooves, a plurality of second wire grooves, a plurality of first lead wires and a plurality of second lead wires are arranged, wherein each first lead wire is arranged corresponding to one of the first wire grooves, and laid out on a bottom and sidewalls of a corresponding first wire groove; and each second lead wire is arranged corresponding to one of the second wire grooves, and a plurality of recesses and protrusions are arranged alternately on a bottom surface of each second wire groove along an extension direction of the each second wire groove, wherein each second lead wire is laid out on surfaces of recesses and protrusions on a bottom surface of a corresponding second wire groove.