Array Substrate Wiring Structure for Low-Resistance Display Lines
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Solution Overview
Problem
Current display products with high resolution and high refresh rates face challenges in reducing metal wiring resistance without increasing thickness, which leads to short circuits and increased production costs, particularly in liquid crystal display panels with 8K or 16K resolution.
Innovation Solution
The array substrate design includes a first conductive layer with a reduced thickness and a second conductive layer with a larger thickness, where the first conductive layer's wiring pattern is connected to the second conductive layer's interconnection pattern through via holes, increasing the cross-sectional area of the data lines and gate lines, thereby reducing resistance and preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of metal wiring layers is increased to reduce resistance, then electrical conductivity is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from a single-layer thick conductive structure to a multi-layer stacked conductive structure. The first conductive layer (with data lines) and second conductive layer (with auxiliary lines) are stacked vertically, allowing current to flow through multiple paths and effectively reducing resistance without increasing the thickness of any single layer. This dimensional change from 2D to 3D conductive pathways solves the contradiction between conductivity and manufacturing complexity.
Solution Approach 2:
The conductive system is segmented into multiple independent conductive layers. The first conductive layer contains the primary data lines, while the second conductive layer contains auxiliary lines that provide additional current paths. This segmentation allows each layer to be manufactured and controlled independently, reducing the complexity of manufacturing a single ultra-thick layer while achieving the desired conductivity through combined effect.
2Reliability
If the thickness of metal wiring layers is increased to reduce resistance, then electrical conductivity is improved, but short circuit risk increases
Solution Approach 1:
By stacking conductive layers vertically with insulating layers in between, the patent creates separated current pathways in the vertical dimension. The first and second conductive layers are isolated by an insulating layer, preventing lateral short circuits that would occur in a single thick layer. The current flows through controlled vertical via holes rather than risking uncontrolled lateral leakage paths.
Solution Approach 2:
An insulating layer is introduced as an intermediary between the first and second conductive layers. This insulating layer acts as a barrier that prevents direct electrical contact between the stacked conductive layers, eliminating the risk of short circuits between them while still allowing the system to benefit from multiple conductive pathways for reduced resistance.
3Reliability
If the thickness of metal wiring layers is increased to reduce resistance, then electrical conductivity is improved, but production cost increases
Solution Approach 1:
The conductive system is divided into multiple standard-thickness layers that can be manufactured using conventional thin-film deposition processes. Each layer is formed with standard manufacturing tolerances and thicknesses, avoiding the need for specialized ultra-thin or ultra-thick layer processing equipment. This segmentation into manufacturable units reduces production costs compared to creating a single thick layer.
Solution Approach 2:
The multi-layer conductive structure serves multiple functions simultaneously: the first conductive layer provides primary signal transmission, the second conductive layer provides auxiliary current paths and compensation, and the stacked structure enables better heat dissipation and stress distribution. This multi-functionality justifies the additional manufacturing steps by providing multiple benefits beyond just resistance reduction.
Data Source
AI summary
An array substrate includes: a base; gate lines and data lines on the base; multiple pixel units each including a thin film transistor; first and second conductive layers with a first insulating layer therebetween. The first conductive layer includes a first wiring pattern, the second conductive layer includes a first interconnection pattern, orthographic projections of the first wiring pattern and the first interconnection pattern on the base are at least partially overlapped. The first wiring pattern is connected with the first interconnection pattern through a via hole. Each of part of data lines is located in the first conductive layer and has an auxiliary line formed by the first interconnection pattern in the second conductive layer. The first wiring pattern includes the data lines; at least one of the data line and the first interconnection pattern is connected to a source of the thin film transistor.


