Array Substrate Wiring Protection During Etching

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Solution Overview

Problem

The existing array substrate structure of display panels faces yield and reliability issues due to damage of wirings during the etching process, particularly when exposing material layers, which affects the fabricating process.

Innovation Solution

The solution involves forming a substrate with patterned conductive and insulating layers, where semiconductor and inorganic insulating protective patterns are strategically placed in the wiring region to protect the wirings from damage during etching, using a method that includes forming first and second patterned protective layers with contact holes to expose drain electrodes and using these patterns as etching masks to prevent wiring damage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If etching processes are performed to expose material layers for fabricating the array substrate structure, then the fabricating process can proceed, but the wirings under the protecting layer are damaged

Engineering Contradiction:
Improvefabricating processVSAvoidwiring integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by forming protective patterns (comprising protective layers and etching masks) on the wirings in the wiring region before performing etching processes. This pre-protection ensures that when subsequent etching steps expose material layers in the display region, the wirings remain intact and undamaged, thus maintaining both manufacturability and wiring integrity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses etching masks as intermediary elements that are deposited over the wirings in the wiring region. These etching masks serve as mediators that allow the etching process to proceed in the display region while physically protecting the wirings from damage, enabling the etching to expose material layers without compromising wiring integrity

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If wirings are exposed during etching process, then material layers can be defined, but yield of the array substrate structure is adversely impacted

Engineering Contradiction:
Improvematerial layer definitionVSAvoidyield
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-forming protective patterns and etching masks on the wirings before performing etching processes. This ensures that when etching exposes material layers with high precision in the display region, the wirings remain protected, preventing damage that would reduce yield, thus achieving both precise material layer definition and high productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The etching masks serve as intermediary protective layers that enable precise etching of material layers in the display region while simultaneously protecting the wirings in the wiring region. This dual function allows high manufacturing precision without compromising yield, as the intermediaries prevent wiring damage that would otherwise occur during material layer definition

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8772780B2Array substrate structure of display panel and method of making the same
Publication Date: 2014.07.08 AU OPTRONICS CORP
  • US8772780B2 patent drawing
  • US8772780B2 patent drawing
  • US8772780B2 patent drawing

AI summary

An array substrate structure of a display panel includes a substrate, a plurality of first wirings, a first patterned insulating layer, a plurality of second wirings, a plurality of first protective patterns, and a plurality of second protective patterns. The substrate has a wiring region. The first wirings are disposed in the wiring region. The first patterned insulating layer is disposed on the first wirings. The second wirings are disposed on the first patterned insulating layer. The first protective patterns are disposed in the wiring region and disposed on the corresponding second wiring, respectively, where the first protective pattern includes a semiconductor material. The second protective patterns are disposed on the corresponding first protective pattern, respectively, where the second protective pattern includes an inorganic insulating material.