Array Substrate Zig-Zag Gate Line Routing for Dot Inversion
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Solution Overview
Problem
The existing array substrates without a frame area face challenges in implementing a zig-zag structure due to the placement of gate lines and data lines, which restricts the electrical connections necessary for the dot inversion effect, leading to increased power consumption and reduced display quality.
Innovation Solution
The array substrate design includes a configuration where first and second TFTs are arranged with their electrodes and gates positioned relative to data and gate lines in a zig-zag pattern, allowing for electrical connections that mimic the zig-zag structure even when gate lines and data lines share a metal layer, enabling efficient signal polarity inversion without a frame area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If gate lines and data lines are placed in the same metal layer, then device complexity is reduced, but the ability to implement zig-zag electrical connections for dot inversion is compromised
Solution Approach 1:
The patent segments the gate lines into two separate metal layers (first gate lines in one layer, second gate lines in another layer), allowing independent routing of each gate line set to achieve zig-zag electrical connections while maintaining a simplified overall structure without requiring additional frame area
Solution Approach 2:
The patent utilizes the vertical dimension by placing gate lines in different metal layers, enabling zig-zag electrical connections through vertical stacking rather than horizontal routing, thus achieving dot inversion capability without increasing planar device complexity
2Adaptability or versatility
If a frame area is used to accommodate gate drive circuits, then zig-zag structure can be implemented, but the display area is reduced
Solution Approach 1:
The patent moves the gate drive circuit functionality into the display area by utilizing multiple metal layers for gate lines, enabling zig-zag structure implementation without requiring additional frame area, thus maintaining full display area utilization
3Ease of manufacture
If TFTs in odd and even rows connect to data lines at the same side, then manufacturing is simplified, but power consumption increases due to inability to implement dot inversion
Solution Approach 1:
The patent segments the gate line routing into two separate sets (first gate lines and second gate lines) in different metal layers, with TFTs in odd rows connecting to one set and TFTs in even rows connecting to the other set, enabling dot inversion capability while maintaining manufacturing simplicity
Solution Approach 2:
The patent implements dot inversion by inverting the connection pattern between TFT rows and data lines through the zig-zag structure, where odd and even rows connect to data lines at opposite sides, thereby reducing power consumption while maintaining ease of manufacture
Data Source
AI summary
The disclosure relates to an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes a plurality of data lines and a plurality of first gate lines, a plurality of first pixel units and a plurality of second pixel units; a plurality of second gate lines; a first TFT and a second TFT, where a first electrode of the first TFT is disposed at one side of the second gate line, the gate and the second electrode of the first TFT is disposed at the other side of the second gate line, the gate, the first electrode, the second electrode and the active layer of each second TFT are disposed at the same side of the second gate line, where the first electrodes of the first TFT and the second TFT are electrically connected to the date lines respectively.