Array Substrate Switch Circuit Layout for Narrower Subpixel Pitch
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Solution Overview
Problem
The increasing pixel density in display devices requires an efficient layout of circuits in the surrounding area to maintain effective signal supply, which existing technologies have not adequately addressed.
Innovation Solution
The implementation of a switch circuit with transistors and signal lines in different layers, allowing for efficient signal switching and reduced circuit width, enabling a high-definition display device with narrowed subpixel pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the pixel density is increased to achieve high-definition display, then the display quality is improved, but the circuit layout in the surrounding area becomes insufficient and signal supply becomes inadequate
Solution Approach 1:
The patent applies three-dimensional stacking technology to arrange transistors and signal lines in different layers. Specifically, first and second transistors are positioned in different layers, and signal lines are routed through multiple layers to connect these transistors. This vertical arrangement in the Z-direction enables efficient signal supply to high-density pixels while maintaining compact surrounding area circuit layout, effectively resolving the contradiction between increased pixel density and circuit layout efficiency.
2Length of moving object
If the circuit width is reduced to accommodate higher pixel density, then the subpixel pitch is narrowed, but the signal switching capability becomes insufficient
Solution Approach 1:
The patent implements multi-layer signal routing where signal lines extend through different layers to connect transistors positioned in separate layers. This three-dimensional signal path allows adequate signal switching capability to be maintained within a reduced horizontal circuit width, enabling narrowed subpixel pitch while preserving reliable signal transmission and switching functions.
Solution Approach 2:
The patent combines multiple circuit functions into a compact three-dimensional structure. First and second transistors along with their associated signal lines are integrated across different layers, merging what would traditionally require separate planar spaces into a unified vertical arrangement. This consolidation enables reduced circuit width while maintaining complete signal switching capability through the stacked configuration.
Data Source
AI summary
According to one embodiment, an array substrate includes signal lines and a switch circuit. The signal lines include first and second signal lines. The switch circuit includes a circuit unit including first and second transistors, a first input line, first and second select lines, a first output line which intersects with the first select line, and a second output line which intersects with the first select line. A first intersection of the first output line which intersects with the first select line and a second intersection of the second output line which intersects with the first select line are formed in different layers.