Array-Under-Periphery Memory Structure for High Thermal Processing
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Solution Overview
Problem
Traditional 3D memory manufacturing processes are limited by the restriction of not allowing high thermal processes to avoid damage to periphery elements, which hinders the optimization of array device performance and reliability.
Innovation Solution
A memory structure with an array-under-periphery configuration that allows high thermal processes during manufacturing, utilizing a substrate with an array portion and a periphery portion connected by contacts, where the array portion includes memory elements and connection layers, and the periphery portion includes thin-film transistors and metal layers, enabling improved device performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional periphery first process is used to protect periphery elements, then periphery element integrity is maintained, but high thermal process cannot be applied and array device performance cannot be optimized
Solution Approach 1:
The memory device is divided into two distinct portions: an array portion and a periphery portion. This segmentation allows different processing conditions to be applied to each portion independently, enabling high thermal processes on the array portion while protecting the periphery portion from thermal damage.
Solution Approach 2:
The patent transitions from a planar layout to a three-dimensional stacked architecture where the array portion is positioned below the periphery portion. This vertical arrangement allows the array to undergo high thermal processing while the periphery remains protected, effectively using the third dimension to resolve the thermal conflict.
2Area of stationary object
If 3D stacked memory structure is used to increase memory capacity, then chip area is reduced, but manufacturing process complexity increases
Solution Approach 1:
Instead of the traditional periphery-first approach where periphery elements are formed before array elements, this patent inverts the sequence by forming the array portion first and then adding the periphery portion. This inversion simplifies the manufacturing process by allowing standard high thermal processes to be used for the array without requiring special protective measures for the periphery.
Data Source
AI summary
A memory structure is provided. The memory structure includes a substrate, an array portion disposed on the substrate, a periphery portion disposed on the array portion, and a plurality of contacts connecting the array portion to the periphery portion.