Array Substrate Via Formation Using Two-Stage ICP Etching
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Solution Overview
Problem
The existing methods for preparing array substrates face challenges such as deep etching depth and long etching time, which increase polymer deposition in vias, affecting subsequent metal lapping and product yield and quality, and also involve complex manufacturing processes and high costs due to the need for multiple vias and masking steps.
Innovation Solution
A method that forms a via by sequentially depositing and etching multiple insulation layers in a single patterning process, reducing etching time and complexity by using Inductively Coupled Plasma (ICP) etching with specific gas mixtures like NF3 and O2, and SF6 and O2, to create a sub-via and then a via, thereby reducing the number of etching steps and masking processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If deep etching is used to penetrate through multiple insulation layers, then via formation is achieved, but etching time increases and polymer deposition affects subsequent metal lapping
Solution Approach 1:
The patent divides the etching process into two stages: first forming a sub-via that penetrates through the third and second insulation layers, then forming the final via by etching through the remaining first insulation layer. This segmentation reduces the depth of each etching step, decreasing polymer deposition and improving via quality while reducing total etching time.
Solution Approach 2:
The patent performs preliminary etching to form a sub-via before completing the via formation. This preliminary action creates a guided path for subsequent etching, ensuring precise via formation while minimizing polymer deposition in the final etching step.
2Reliability
If multiple vias and masking steps are used to form via structures, then electrical connection is achieved, but manufacturing process complexity and cost increase
Solution Approach 1:
The patent combines multiple etching steps into a unified two-stage process where the sub-via formation and final via formation are integrated. This merging reduces the number of separate masking steps and simplifies the manufacturing process while maintaining reliable electrical connection through the via structure.
Solution Approach 2:
The via structure formed by this patent serves multiple functions: it provides electrical connection between metal layers, acts as a template for subsequent etching steps, and ensures precise alignment through the overlapping orthographic projection with the conductive portion. This multi-functionality reduces the need for additional separate processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces etching time, prevents polymer deposition, improves product yield and quality, and decreases manufacturing costs by simplifying the process and reducing the number of masking steps required.
Implementation Method 1
using Inductively Coupled Plasma (ICP) etching with specific gas mixtures like NF3 and O2, and SF6 and O2
Data Source
AI summary
Disclosed is a preparation method for an array substrate including: forming a first conductive portion on a substrate; sequentially forming a first insulating layer, a second insulating layer and a third insulating layer on the side of the first conductive portion that faces away from the substrate; forming, through one-time patterning process, a first sub-via that penetrates through the third insulating layer, the second insulating layer and a first part of the first insulating layer; forming a fourth insulating layer on the side of the third insulating layer that faces away from the substrate; etching and removing the fourth insulating layer and the first insulating layer of the second thickness that are at the first sub-via, so as to form a first via; and forming a first connection electrode on the side of the fourth insulating layer that faces away from the substrate.