Arrayed TDC Matched Delay Lines for Low-Noise Timing Precision
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Solution Overview
Problem
Highly parallel time-to-digital converter (TDC) systems face significant power supply noise and challenges in delivering accurate and aligned clocks, especially at high clock frequencies and fine clock skews, which affect the accuracy and reliability of arrayed active imaging systems.
Innovation Solution
The proposed solution involves sampling matched delay lines to generate high-resolution timing, allowing a single clock reference to be delivered to arrayed TDCs, reducing power supply noise by only the clock tree switching during operation, and utilizing a delay-locked loop to control the delay lines, ensuring accurate timing measurements across circuit variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If highly parallel TDC systems are used to improve timing measurement capability, then measurement precision is improved, but power supply noise increases
Solution Approach 1:
The system divides the timing measurement function into multiple parallel TDC channels, each handling a portion of the measurement task. This segmentation allows independent operation of each channel with controlled power consumption, reducing overall noise while maintaining high measurement precision through parallel processing
Solution Approach 2:
The TDC system operates in periodic cycles, activating measurement functions only when timing events occur rather than continuous operation. This periodic activation reduces power supply noise by minimizing the time during which power-consuming operations are active, while still achieving high measurement precision when needed
2Measurement precision
If arrayed TDCs are used to improve timing measurement capability, then measurement precision is improved, but clock delivery alignment becomes more difficult
Solution Approach 1:
The system merges the clock distribution function into a unified clock tree structure that serves all TDC channels simultaneously. This consolidation simplifies clock delivery alignment by ensuring all channels receive synchronized clock signals from a single source, reducing the complexity of maintaining alignment across multiple independent clock paths
Solution Approach 2:
A centralized clock management unit acts as an intermediary between the clock source and individual TDC channels. This intermediary ensures precise clock distribution and alignment to all channels, simplifying the overall system by centralizing the complex clock synchronization function rather than requiring each channel to manage its own clock alignment
3Reliability
If multiple clock references are delivered to arrayed TDCs, then each TDC can operate independently, but device complexity increases
Solution Approach 1:
A single clock reference is designed to serve multiple functions and all TDC channels simultaneously through a unified distribution network. This universal clock source maintains operational independence of each TDC while reducing device complexity by eliminating the need for multiple separate clock references and their associated distribution infrastructure
Data Source
AI summary
Methods and apparatus for an arrayed time to digital converter (TDC) having matched delay line sampling. In embodiments, a TDC includes a coarse counter circuit to provide an event coarse timing measurement for an event, a coarse counter delivery network to deliver a count value in the coarse counter circuit to a memory storage element circuit, and an array of matched delay lines to provide an event fine timing measurement to the memory storage element circuit. An array of event sample signal generators can generate signals for the event and an array of encoders can encode fine timing measurement information from the memory storage element circuit, where an output of the encoder and the event coarse timing measurement information provide a timestamp for the event. A global delay-locked loop can incorporate a matched delay line coupled to the array of matched delay lines.