Algorithmic Reactive Testbench for Analog Circuit Verification

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Solution Overview

Problem

Existing analog integrated circuit design verification systems lack efficient communication and data sharing between testbenches, requiring manual data transfer and limited simultaneous operation, which hampers the reactive testing process.

Innovation Solution

The Algorithmic Reactive Testbench (ART) system allows for the instantiation and operation of multiple analog testbenches within a program, where properties can be dynamically influenced by prior analyses, enabling a reactive network that automatically updates and communicates through assignment statements, allowing flexible and programmatic control over test objects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If manual data transfer is used between testbenches, then data sharing is possible, but verification efficiency is reduced and time consumption increases

Engineering Contradiction:
Improveverification efficiencyVSAvoiddata transfer time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

Multiple testbenches are merged into a single unified testbench structure that can operate simultaneously. The patent combines multiple testbench functionalities into one integrated environment where testbenches share common resources and communicate through defined interfaces, eliminating the need for manual data transfer between separate testbench sessions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

A data sharing mechanism acts as an intermediary between testbenches, allowing automatic data exchange. The patent implements shared memory structures and communication protocols that enable testbenches to automatically share test vectors, results, and configuration data without manual intervention, resolving the time loss associated with manual data transfer.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If testbenches operate independently, then testbench stability is maintained, but communication and data sharing between testbenches is limited

Engineering Contradiction:
Improvetestbench communication capabilityVSAvoidtestbench integration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The unified testbench is segmented into independent testbench modules that can operate autonomously while maintaining communication capabilities. Each testbench module retains its own configuration and execution logic, but they are organized within a hierarchical structure that enables controlled interaction through standardized interfaces, balancing independence with communication capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The testbench architecture implements universal communication interfaces and shared data structures that enable any testbench to communicate with any other testbench. The patent creates a multi-functional framework where a single testbench structure can serve multiple purposes and interact with various other testbenches through common protocols, reducing integration complexity despite enhanced adaptability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If multiple testbenches are operated simultaneously, then verification productivity increases, but system resource consumption increases

Engineering Contradiction:
Improveverification throughputVSAvoidcomputational resource consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The testbench system implements dynamic resource allocation and adaptive parallel execution. The patent allows the system to dynamically adjust the number and type of testbenches running simultaneously based on available resources and verification priorities. Testbenches can be activated or deactivated dynamically, and resource-intensive operations can be scheduled during periods of lower demand, enabling high productivity while managing resource consumption efficiently.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS7853908B2Algorithmic reactive testbench for analog designs
Publication Date: 2010.12.14 NAT SEMICON CORP
  • US7853908B2 patent drawing
  • US7853908B2 patent drawing

AI summary

An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are instantiated and operated as prescribed in an algorithmic reactive testbench program, and the properties of the unit testbenches (test objects) can be influenced by prior analysis of themselves or other tests. The test object may also contain various properties including information reflecting the status of the test object. The modification of a property of a test object is an act of communication in the ART system from the algorithmic reactive testbench program to the test object.