Artificial Neuron Processing Apparatus Reducing Multiplier Count
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Solution Overview
Problem
Current neural networks implemented in integrated circuits require significant memory and complex hardware due to the large number of multipliers needed for weight and synapse value multiplication, leading to increased cost, size, and power consumption.
Innovation Solution
A processing apparatus and method that uses a parser, lookup array, and MAC circuit to reduce the number of multipliers by packing non-zero weight values into packets, indexing synapse values, and performing parallel processing to compute the propagation function efficiently, thereby reducing memory size and hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the propagation function is computed directly with N multipliers for each synapse value, then the neural network can process all synapse values, but the number of multipliers and memory size increase significantly
Solution Approach 1:
The patent extracts only the non-zero weight values from the weight matrix and processes only those synapse values corresponding to non-zero weights. By identifying and extracting the subset of relevant synapse values (those with non-zero weights), the system avoids unnecessary multiplication operations with zero weights, thereby reducing the number of multipliers from N to K where K is the number of non-zero weights per neuron.
Solution Approach 2:
The patent segments the weight matrix into multiple packets, where each packet contains a subset of non-zero weight values and their corresponding synapse value indices. This segmentation allows the system to process weight values in smaller batches, reducing the memory size required to store all weights simultaneously and enabling more efficient parallel processing with fewer multipliers.
2Productivity
If the weight values are stored in full memory for all N synapses, then all weight values are available, but the memory size becomes large
Solution Approach 1:
The patent extracts and stores only the non-zero weight values in memory, rather than storing all N weight values including zeros. By identifying the subset of non-zero weights and storing only those values along with their corresponding synapse indices, the memory size is reduced from N weight values to K non-zero weight values, where K < N.
Solution Approach 2:
The patent segments the weight values into multiple packets that are loaded into memory in batches. Each packet contains a subset of non-zero weight values and their corresponding synapse indices. This segmentation allows the system to process weights in smaller chunks, reducing the peak memory size requirement while maintaining access to all necessary weight values.
3Productivity
If more neurons are placed on the integrated circuit, then the neural network capacity increases, but the area per neuron decreases
Solution Approach 1:
By extracting and processing only non-zero weight values, the patent reduces the computational resources (multipliers and memory) required per neuron. This reduction in resource requirements per neuron allows more neurons to be packed into the same integrated circuit area, thereby increasing the overall neural network capacity without proportionally increasing the chip area.
Solution Approach 2:
The patent segments the processing into multiple packets that can be handled by a smaller number of multipliers. This segmentation reduces the per-neuron hardware footprint by eliminating the need for dedicated multipliers for zero-weight synapses, thereby freeing up area for additional neurons on the integrated circuit.
Data Source
AI summary
A processing apparatus applied in an artificial neuron is disclosed. The processing apparatus comprises a parser, a lookup array, a summing circuit and a MAC circuit. The parser parses one of M packets to extract a non-zero weight value from a header of the one packet, to identify a plurality of bit positions with a specified digit from a payload of the one packet, and to output the non-zero weight value and the bit positions in parallel. The lookup array contains N synapse values and is indexed by the bit positions in parallel to generate a plurality of match values. The summing circuit sums up the match values to generate a sum value. The MAC circuit generates a product of the non-zero weight value and the sum value, and generates an accumulate value based on the product and at least one previous accumulate value.