Asynchronous SAR ADC Clocking for Meta-Stability-Limited Conversion
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Solution Overview
Problem
Asynchronous successive approximation register analog-to-digital converters (ASAR ADCs) face challenges in completing N-bit conversions due to meta-stability effects, leading to longer data comparison times that exceed the allowable time of external clocks, especially at low frequencies, resulting in incomplete conversion of analog data to digital signals.
Innovation Solution
The implementation of a clock generator that produces a clock signal with a higher frequency than the external clock, coupled with a logic control unit, sample and hold circuit, digital-to-analog converter, and comparator, allows for efficient sampling and comparison of analog signals, ensuring timely completion of N-bit conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ASAR ADC performs multiple bit data processing using prior art methods, then the conversion process can be completed, but the total data comparison time exceeds the allowable time of the external clock due to meta-stability effects
Solution Approach 1:
The patent changes the frequency parameter of the clock signal used internally. A clock generator produces an internal clock signal with frequency higher than the external clock frequency, allowing the ADC to complete multiple bit comparisons within the external clock period. This parameter change resolves the time constraint while maintaining conversion accuracy.
2Use of energy by moving object
If the external clock frequency is low, then power consumption is reduced, but the ASAR ADC cannot complete data comparison on time
Solution Approach 1:
The patent segments the clocking function into two levels: the external low-frequency clock that triggers conversion and consumes minimal power, and an internal high-frequency clock generated by the clock generator that performs the actual bit comparisons. This segmentation allows low power consumption while maintaining high conversion speed.
Solution Approach 2:
The clock generator acts as an intermediary between the external low-frequency clock and the internal comparison process. It receives the low-frequency external clock signal and generates a higher frequency internal clock signal, mediating between power consumption requirements and conversion speed requirements.
3Adaptability or versatility
If N-bit conversion is performed using prior art ASAR ADC, then analog data can be converted to digital signals, but meta-stability effects cause the conversion to fail at low external clock frequencies
Solution Approach 1:
The patent changes the time parameter available for comparison by using a higher frequency internal clock. This allows the ADC to complete N-bit conversions successfully even at low external clock frequencies, preventing meta-stability effects and improving conversion reliability across different operating conditions.
Data Source
AI summary
An asynchronous successive approximation register analog-to-digital converter includes a clock generator, a logic control unit, a sample and hold circuit, a digital-to-analog converter and a comparator. The clock generator is used to generate a clock signal. The logic control unit is for generating a sample and hold clock according to the clock signal. The sample and hold circuit is for sampling an analog signal according to the sample and hold clock to obtain and hold a sampling signal. The digital-to-analog converter is for generating a reference value according to a digital value transmitted from the logic control unit. The comparator is for generating a comparison value according to the sampling signal and the reference value.