Ascon Hardware Engines for Secure High-Bandwidth Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current graphics processing units (GPUs) face challenges in efficiently processing graphics data due to limitations in parallel processing capabilities, particularly in SIMT architectures, which can lead to inefficiencies in executing program instructions synchronously.
Innovation Solution
Implementing Ascon-based cryptography techniques for secure high-bandwidth interconnects within GPUs to enhance data integrity and processing efficiency, utilizing Ascon hardware engines for MAC tag computation with low latency, and employing secure I/O operations through Trusted Execution Environment (TEE)-I/O support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Ascon-based cryptography is implemented for secure high-bandwidth interconnects, then data security and integrity are improved, but device complexity increases
Solution Approach 1:
The patent divides the cryptographic protection into separate functional components: Ascon hardware engines for MAC tag computation, Trusted Execution Environment for security management, and secure I/O operations. This segmentation allows each component to be optimized independently while working together to provide comprehensive data security without overwhelming complexity in a single system.
Solution Approach 2:
The patent introduces Trusted Execution Environment as an intermediary layer between the cryptographic operations and the rest of the system. This mediator manages the complexity of key management, authentication, and secure communication protocols, shielding the main system from cryptographic complexity while ensuring data security and integrity across high-bandwidth interconnects.
2Productivity
If Ascon hardware engines are used for MAC tag computation, then processing efficiency is improved, but device complexity increases
Solution Approach 1:
The patent replaces software-based cryptographic operations with dedicated Ascon hardware engines that perform MAC tag computation at the hardware level. This substitution eliminates the need for complex software cryptographic libraries and manual key management, significantly improving processing efficiency while the modular hardware design keeps the complexity increase manageable through standardized cryptographic accelerator patterns.
3Reliability
If secure I/O operations through TEE are implemented, then data integrity is improved, but ease of operation decreases
Solution Approach 1:
The Trusted Execution Environment provides self-service security functions where the system automatically manages cryptographic operations, key rotation, and authentication without requiring manual intervention. The TEE handles security protocols transparently, maintaining data integrity while keeping the user interface simple and the operational workflow unchanged for most applications.
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
An apparatus to facilitate Ascon-based protections for high bandwidth interconnects is disclosed. The apparatus includes Ascon hardware circuitry of a chiplet hosting processing cores, comprising: an input multiplexer to receive input data for the Ascon hardware circuitry; a first pipeline stage hardware circuitry to perform at least one of rounds zero through three of an Ascon cryptography process or rounds eight through eleven of the Ascon cryptography process on the input data based on a mode input; a first pipeline register to receive a first output of the first pipeline stage hardware circuitry; a second pipeline stage hardware circuitry to perform rounds four through seven of the Ascon cryptography process on the first output; and a second pipeline register to store second output of the second pipeline stage hardware circuitry to pass to the input multiplexer for additional processing by the first pipeline stage hardware circuitry.