Ascon Hardware Pipeline for Secure High-Bandwidth Interconnects

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Solution Overview

Problem

Current graphics processing units (GPUs) face challenges in efficiently processing graphics data due to the limitations of fixed function computational units and the need for improved parallel processing techniques, particularly in SIMT architectures, which can be enhanced by implementing Ascon-based cryptography for secure high-bandwidth interconnects.

Innovation Solution

The integration of Ascon-based cryptography within GPUs to secure high-bandwidth interconnects, utilizing a MAC tag computation engine for data tampering protection, enhances data security and processing efficiency by ensuring secure and reliable communication between GPU components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Ascon-based cryptography is integrated into GPUs to secure high-bandwidth interconnects, then data security is improved, but device complexity increases

Engineering Contradiction:
Improvedata securityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The cryptographic functionality is segmented into a dedicated MAC tag computation engine separate from the main GPU processing units. This allows the security function to be implemented as an independent hardware module that processes authentication tags without interfering with the primary graphics processing operations, thus improving data security while managing device complexity through functional separation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A MAC tag computation engine is introduced as an intermediary component between the data transmission and authentication functions. This intermediary hardware module computes authentication tags for data packets traversing the high-bandwidth interconnect, providing cryptographic protection without requiring modifications to the core GPU architecture or processing units.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a MAC tag computation engine is added for data tampering protection, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvedata tampering protectionVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The MAC tag computation engine is merged with the existing GPU hardware architecture, integrating the cryptographic authentication functionality into the established manufacturing process. By combining the security functions with the existing data path infrastructure, the patent leverages existing manufacturing capabilities while adding the necessary authentication capabilities, thus improving reliability without proportionally increasing manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If Ascon-based cryptography is implemented for secure communication, then data transmission security is improved, but processing efficiency may deteriorate

Engineering Contradiction:
Improvedata transmission securityVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Authentication tags are computed in advance during data transmission preparation, allowing the MAC tag computation engine to process security operations before the data reaches its destination. This preliminary authentication action ensures that security checks are performed without blocking the main data processing pipeline, thus improving data transmission security while maintaining processing efficiency through asynchronous security operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250291592A1Ascon-based protections for high bandwidth interconnects
Publication Date: 2025.09.18 INTEL CORP
  • US20250291592A1 patent drawing
  • US20250291592A1 patent drawing
  • US20250291592A1 patent drawing

AI summary

An apparatus to facilitate Ascon-based protections for high bandwidth interconnects is disclosed. The apparatus includes Ascon hardware circuitry of a chiplet hosting processing cores, comprising: an input multiplexer to receive input data for the Ascon hardware circuitry; a first pipeline stage hardware circuitry to perform at least one of rounds zero through three of an Ascon cryptography process or rounds eight through eleven of the Ascon cryptography process on the input data based on a mode input; a first pipeline register to receive a first output of the first pipeline stage hardware circuitry; a second pipeline stage hardware circuitry to perform rounds four through seven of the Ascon cryptography process on the first output; and a second pipeline register to store second output of the second pipeline stage hardware circuitry to pass to the input multiplexer for additional processing by the first pipeline stage hardware circuitry.