ASIC Acceleration Unit Interconnection to Address Bandwidth Limits
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Solution Overview
Problem
The challenge of designing an interconnection scheme between ASICs to improve computing power and achieve efficient processing of massive data in a high-performance processor cluster is significant due to the limitations of data transmission bandwidth in multi-card networks.
Innovation Solution
An acceleration unit composed of M acceleration cards, each with internal and external connection ports, forms a logical matrix or multi-layer structure with interconnected acceleration units, creating a ring structure and hybrid stereo network to enhance computing power and minimize time delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a plurality of ASIC acceleration chips are used to obtain stronger computing power, then the computing power of the system is improved, but the data transmission bandwidth requirement increases, putting a great challenge to the data transmission bandwidth of the ASIC
Solution Approach 1:
The system segments the acceleration function into multiple independent ASIC acceleration chips, each capable of independent operation. This segmentation allows the computing workload to be distributed across multiple chips, thereby increasing overall computing power while managing data transmission bandwidth through parallel processing paths
Solution Approach 2:
The patent introduces a multi-dimensional interconnection architecture that goes beyond traditional single-plane connections. By creating multiple connection dimensions and pathways between ASIC chips, the system increases effective data transmission bandwidth without requiring a proportional increase in single-link bandwidth, thus resolving the bandwidth bottleneck while maintaining enhanced computing power
2Power
If multiple ASICs are interconnected to form a multi-card network, then the computing power is enhanced, but the complexity of the interconnection scheme increases
Solution Approach 1:
The interconnection scheme employs universal connection interfaces and standardized communication protocols that can be applied across different ASIC chips and configurations. This multi-functionality allows the same interconnection architecture to support various computing power scales, reducing the complexity that would otherwise arise from designing specialized connection schemes for different configurations
Solution Approach 2:
The patent implements a hierarchical nested interconnection structure where local interconnections within groups are nested within broader interconnections between groups. This nesting approach organizes the complexity into manageable layers, where each layer handles a specific scope of communication, thereby reducing the overall system complexity while still enabling enhanced computing power through multiple interconnected ASICs
Data Source
AI summary
The present disclosure relates to an acceleration unit, an acceleration assembly, an acceleration device, and an electronic device. The application unit is included in a combined processing device. The combined processing apparatus further includes an interconnection interface and other processing device. The application unit interacts with other processing device to jointly complete a computing operation specified by a user. The combined processing device further includes a storage device. The storage device is connected to the acceleration unit and other processing devices, respectively. The storage device is used for data services of the acceleration unit and other processing devices. With the help of the content of the present disclosure, high-speed processing of massive data may be realized.