ASIC Hardware Accelerator for Bluetooth Audio LD-MDCT Encoding

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Solution Overview

Problem

Current Bluetooth audio technologies face challenges in reducing power consumption and processing load while maintaining high sound quality, especially with increasing data processing demands.

Innovation Solution

An application-specific integrated circuit (ASIC) is designed with a hardware accelerator that performs low-delay modified discrete cosine transform (LD-MDCT) and inverse modified discrete cosine transform (LD-IMDCT) operations using multi-level discrete Fourier transforms, specifically Winograd Fourier transforms, to accelerate encoding and decoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If AAC coding technology is used to achieve better sound quality, then sound quality is improved, but energy consumption increases significantly

Engineering Contradiction:

Improvesound qualityVSAvoidenergy consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent replaces software-based AAC encoding/decoding with a dedicated hardware accelerator that implements MDCT operations using specialized circuitry. This hardware substitution eliminates the need for complex software algorithms, significantly reducing energy consumption while maintaining audio quality through optimized hardware signal processing

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware accelerator divides the complex MDCT operation into separate functional modules: input buffering, windowing, bit-reversal permutation, butterfly operations, and output processing. This segmentation allows each module to be optimized independently for low power consumption while collectively achieving high-quality audio encoding/decoding

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If higher audio quality is pursued, then sound quality is improved, but data processing load increases significantly

Engineering Contradiction:

Improvesound qualityVSAvoiddata processing load

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent substitutes general-purpose CPU/DSP processing with a dedicated hardware accelerator that performs MDCT operations in parallel using fixed-function circuitry. This hardware implementation processes audio data much faster than software approaches, reducing the data processing load on the main processor while maintaining high audio quality

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The hardware accelerator introduces a dedicated processing dimension separate from the main CPU/DSP. By offloading MDCT operations to this parallel hardware dimension, the system can process audio data without increasing the computational burden on the main processor, effectively decoupling audio quality from processing load

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If pure software optimization is used for LC3 codec, then implementation flexibility is improved, but processing speed and power efficiency deteriorate

Engineering Contradiction:

Improveimplementation flexibilityVSAvoidprocessing speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent replaces software-based LC3 codec implementation with a hardware accelerator that performs MDCT operations at the circuit level. This hardware substitution dramatically increases processing speed while maintaining flexibility through configurable parameters that can be adjusted to match different audio quality requirements and power constraints

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS12340816B2Application-specific integrated circuit for accelerating encoding and decoding, and method therefor

Publication Date: 2025.06.24 BEIJING BAIRUI INTERNET TECH CO LTD

AI summary

An application-specific integrated circuit for accelerated encoding and decoding and a method, which are related to the technical field of Bluetooth mobile communication. The application-specific integrated circuit for accelerated encoding and decoding includes: a hardware accelerator, wherein the hardware accelerator includes a pre-processing and pronation processing module, which performs a pre-processing and pronation processing of data, a discrete Fourier transform module is used for performing a multi-level discrete Fourier transform, in an accelerated low-delay modified discrete cosine transform operation LD-MDCT and/or an accelerated the low-delay inverse modified discrete cosine transform operation LD-IMDCT. The application-specific integrated circuit for accelerated encoding and decoding and a method of the present invention adopts an ASIC application-specific integrated circuit, and adopts multi-level discrete Fourier transforms, so that the complex operations are completed by the ASIC application-specific integrated circuit.