ASIC Beat-Level ECC Decoding for DRAM Data Integrity
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Solution Overview
Problem
Existing memory systems face latency and data rate reduction due to the need for on-die and link ECCs for error correction in DRAM components, which increase costs and reliability burdens.
Innovation Solution
Implementing on-ASIC ECC encoding and decoding on beats of data, where a digital system assembles words of varying lengths, constructs a parity word, and adds it to form a beat, enabling error correction without the need for on-die or link ECCs, using a parity check matrix for decoding and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die and link ECCs are implemented for error correction in DRAM components, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the ECC functionality from the traditional on-die and link locations and relocates it to the ASIC interface. The memory controller ASIC performs both encoding and decoding of ECC codes, separating this function from the DRAM chip itself and the external link, thereby simplifying the overall system architecture while maintaining error correction capability
Solution Approach 2:
The memory controller ASIC is designed to perform multiple functions including both ECC encoding and decoding operations. This multi-functional approach consolidates what would traditionally require separate dedicated ECC circuits in multiple locations into a single versatile component, reducing overall device complexity
2Reliability
If on-die and link ECCs are implemented for error correction, then reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the ECC encoding and decoding functions into a single integrated solution within the memory controller ASIC. This consolidation eliminates the need for separate ECC circuits in the DRAM chip and external link, reducing the total component count and manufacturing complexity, thereby lowering production costs while maintaining comprehensive error correction capability
3Reliability
If traditional ECC scanning and correction procedures are executed, then error detection and correction is achieved, but data rate is reduced due to latency
Solution Approach 1:
The patent implements preliminary ECC encoding at the source (memory controller ASIC) before data is written to or read from the DRAM. This pre-processing approach ensures that error correction capability is built into the data stream in advance, eliminating the need for time-consuming post-read scanning and correction procedures that would otherwise interrupt data flow and reduce data rate
Data Source
AI summary
There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.