ASIC Busbar Layout With Remote Power Phases for Shorter Signal Paths
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Solution Overview
Problem
Existing telecommunications and networking shelf and circuit card assemblies face challenges in reducing signal track length and power consumption due to the conventional arrangement of client and fabric ports, which limits the proximity of QSFP-DD/OSFP connectors to the ASIC, leading to increased power consumption and signal loss.
Innovation Solution
The arrangement of grouped power phases physically distanced from the sides of the ASIC, coupled via busbars, allows for closer positioning of client and fabric ports to the ASIC, reducing track lengths and enabling a generally octagonal configuration with angled and stepped ports, thereby minimizing signal loss and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power phases are arranged around the ASIC chip, then power delivery is improved, but signal track length increases and power consumption increases
Solution Approach 1:
The power phases are extracted from the traditional arrangement around the ASIC and relocated to a distant location on the circuit board. This extraction allows the optical connectors to be positioned close to the ASIC without the power phases interfering with the signal paths, thereby reducing signal track length and power consumption while maintaining power delivery capability through extended trace routing.
Solution Approach 2:
The layout transitions from a two-dimensional arrangement where power phases surround the ASIC to a distributed configuration where power phases are positioned in a separate region. This dimensional reorganization allows signal traces to optimize their paths to the ASIC while power traces extend to reach the distant power phases, resolving the conflict between power delivery and signal integrity.
2Ease of manufacture
If optical connectors are positioned far from ASIC, then power phases can be arranged around ASIC, but signal track length increases leading to higher power consumption
Solution Approach 1:
By extracting the power phases from the immediate vicinity of the ASIC and relocating them to a distant location, the invention enables optical connectors to be positioned optimally close to the ASIC. This extraction resolves the conflict between ease of power phase arrangement and minimization of signal track length, as the power phases no longer constrain connector placement.
3Temperature
If client ports are spaced apart for heatsinks, then cooling is improved, but device complexity and space requirements increase
Solution Approach 1:
Multiple client ports are merged into a shared cage structure rather than being individually spaced apart. This merging allows ports to be positioned closer together while still providing adequate cooling, as the shared cage design enables common cooling infrastructure to serve multiple ports, thereby reducing device complexity and space requirements while maintaining thermal management effectiveness.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
A circuit card assembly includes a printed circuit board, an integrated circuit chip coupled to the printed circuit board, and a plurality of power phases associated with the integrated circuit chip arranged as grouped power phases. One or more power phases of the grouped power phases is physically distanced from a side of the integrated circuit chip associated with physically distanced power phase(s) of the grouped power phases. A shelf system also includes a shelf assembly and a circuit card assembly conformally inserted into the shelf assembly. A plurality of fabric ports are coupled to the printed circuit board and accessible from a rear facing side of the case. A plurality of client ports are accessible from a front facing side of the case.