Standard Cell Mapping Tables for ASIC Technology Migration
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Solution Overview
Problem
The existing methods for migrating ASIC designs from one semiconductor technology to another are time-consuming and require expensive automated software tools, necessitating a more efficient process to minimize design engineer effort and achieve fast turnaround times.
Innovation Solution
A component mapping technique that uses a database of mapping tables to map standard cells from one semiconductor fabrication technology to another, eliminating the need for automatic ASIC synthesis tools and enabling fast Design Technology Co-Optimization (DTCO) solutions for power, performance, and area (PPA) optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If automated synthesis software tools are used to migrate ASIC design from one technology to another, then the migration can be performed automatically, but the process becomes time-consuming and requires expensive tools
Solution Approach 1:
The patent segments the complex automated synthesis process into discrete mapping tables that define relationships between standard cells across different technology nodes. By breaking down the migration into predefined cell mappings rather than full synthesis, the process achieves automation while dramatically reducing time requirements.
Solution Approach 2:
The patent performs preliminary action by pre-establishing mapping tables that contain equivalence relationships between standard cells from different technology libraries. These mappings are created in advance and stored for rapid lookup during migration, eliminating the need for time-consuming real-time synthesis operations.
2Extent of automation
If automated synthesis software tools are used for design migration, then the process can be automated, but expensive tools are required
Solution Approach 1:
The patent uses copying by creating and storing mapping tables that replicate the equivalence relationships between standard cells across technologies. Instead of requiring expensive synthesis tools to perform complex transformations, the system copies predefined mapping relationships and applies them directly to migrate designs, significantly reducing tool cost requirements.
Solution Approach 2:
The patent replaces expensive, complex synthesis software with simple, lightweight mapping table data structures. These mapping tables are inexpensive to create and store, and can be rapidly applied and discarded for different migration scenarios, providing a cost-effective alternative to proprietary synthesis tools.
3Adaptability or versatility
If engineers manually migrate designs to new technology, then customization is possible, but large amounts of time and effort are required
Solution Approach 1:
The patent introduces mapping tables as an intermediary between manual design migration and fully automated synthesis. These tables serve as a bridge that captures the adaptability and customization knowledge that would otherwise require manual engineering, while enabling automated application of that knowledge to dramatically reduce migration time.
4Productivity
If companies have multiple design teams migrating designs simultaneously, then design capacity is increased, but total time and cost expenditure increases significantly
Solution Approach 1:
The patent creates universal mapping tables that can be applied by any design team for any technology migration scenario. These mappings are technology-agnostic and can be reused across multiple teams and projects, allowing simultaneous migrations to proceed independently using the same standardized approach, thereby scaling productivity without proportionally increasing total time or cost.
Data Source
AI summary
A method and system for migrating an existing ASIC design from one semiconductor fabrication process to another are disclosed herein. In some embodiments, a method for migrating the existing ASIC design comprises parsing the gate-level netlist one row at a time into one or more standard cells forming the ASIC design, forming a plurality of mapping tables having mapping rules for mapping the parsed one or more standard cells into equivalent target standard cells implemented in the second semiconductor fabrication process, mapping the parsed one or more standard cells into the equivalent target standard cells using the plurality of mapping tables, and generating a target gate-level netlist describing the ASIC design in terms of the equivalent target standard cells.