ASIC Circuit for Memory-Hard Cryptographic Algorithms
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Solution Overview
Problem
ASIC-resistant cryptographic algorithms face a memory bottleneck due to their reliance on memory access, which limits performance and efficiency, especially in decentralized networks like cryptocurrency mining.
Innovation Solution
The integration of specialized circuits within ASICs to generate data on demand, eliminating the need for external memory access by building the necessary logic to produce required data, thereby bypassing memory constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory-hard algorithms are used to resist ASIC execution, then security and fairness in decentralized networks are improved, but processing speed and system performance deteriorate due to memory access bottlenecks
Solution Approach 1:
The patent extracts the data generation function from external memory and relocates it to specialized on-chip circuits. By taking out the memory dependency and embedding the generation logic directly in the ASIC, the system eliminates the memory access bottleneck while preserving the security properties of memory-hard algorithms.
Solution Approach 2:
The patent introduces specialized circuits as an intermediary between the processor and external memory. These circuits act as mediators that generate required data on-demand using on-chip resources, reducing the need for slow external memory accesses while maintaining algorithmic security requirements.
2Quantity of substance
If external memory is used to store generated data, then data availability is improved, but power consumption and access time increase
Solution Approach 1:
The patent implements a nested architecture where small on-chip memory structures are embedded within the specialized circuits. This nested approach allows the system to store frequently accessed generated data locally, reducing external memory accesses and lowering power consumption while maintaining data availability.
Solution Approach 2:
The patent employs preliminary action by pre-generating data using on-chip circuits before it is needed by the processor. This proactive data generation eliminates wait times and reduces the frequency of power-intensive external memory accesses, thereby lowering overall power consumption.
3Quantity of substance
If data is generated and stored in external memory, then data access capacity is improved, but system bandwidth and processing efficiency deteriorate
Solution Approach 1:
The patent extracts the data generation capability from external memory and embeds it directly in on-chip specialized circuits. This extraction eliminates the need for slow external memory accesses, significantly improving system bandwidth and processing efficiency while maintaining sufficient data storage capacity through on-chip resources.
Solution Approach 2:
The patent replaces the mechanical memory access system (external memory reads) with a computational system (on-chip circuit generation). This substitution transitions from slow physical memory access to faster computational generation, dramatically improving system bandwidth and processing speed.
Data Source
AI summary
An application-specific integrated circuit (ASIC) and method are provided for executing a memory-hard algorithm requiring reading generated data. A processor or state machine executes one or more steps of the memory-hard algorithm and requests the generated data. At least one specialized circuit is provided for generating the generated data on demand in response to a request for the generated data from the processor. Specific embodiments are applied to memory-hard cryptographic algorithms, including Ethash and Equihash.