ASIC Clock Pulse Distribution for Aligned CP and CPN Latches
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Solution Overview
Problem
The existing method of using local inverters in each latch group to generate clock pulse negative/complement (CPN) signals in ASIC cores leads to timing misalignment and on-chip variations, resulting in wider pulse widths and pulse spacing requirements, which degrade the ASIC core frequency and increase time wastage.
Innovation Solution
The solution involves a core stage in an ASIC core that concurrently drives both CP and CPN signals, using a pulse generator with a state element, logic AND gate, and delay element, along with a clock distribution circuit comprising inverters and feedback circuits to ensure perfectly aligned and non-overlapping clock pulses across core stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If local inverters are used in each latch group to generate CPN signals, then the ASIC core can be manufactured with standard components, but timing misalignment and on-chip variations occur causing frequency degradation
Solution Approach 1:
The patent merges the CPN generation function from individual latch-group inverters into a centralized clock distribution circuit. The clock distribution circuit receives a single clock pulse and simultaneously generates both CP and CPN signals, eliminating the distributed inverter architecture that caused timing misalignment and frequency degradation.
2Device complexity
If local inverters are used to generate CPN signals, then device complexity is reduced, but timing alignment between CP and CPN signals deteriorates
Solution Approach 1:
The clock distribution circuit acts as an intermediary between the pulse generator and the latches. It receives the clock pulse and simultaneously generates both CP and CPN signals with precise timing control, ensuring perfect alignment while maintaining manageable circuit complexity through centralized design.
3Reliability
If wider CP pulse is used to accommodate inverter variations, then all latch groups can work correctly, but time wastage increases and frequency decreases
Solution Approach 1:
The patent changes the architectural parameter from distributed inverter-based CPN generation to centralized clock distribution-based simultaneous generation. This parameter change eliminates the need for wider pulse widths to accommodate inverter variations, as the CP and CPN signals are generated concurrently with controlled timing, thereby reducing time wastage and increasing operating frequency.
Data Source
AI summary
Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.