Balanced ASIC Clock Trees for Multi-Voltage Island Skew Control
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Solution Overview
Problem
Existing methods for implementing balanced clock distribution networks on ASICs with voltage islands functioning at multiple operating points of voltage and temperature are inadequate, leading to significant timing penalties and voltage skew, which hinder the ability to maintain a balanced clock tree across varying conditions, resulting in reduced attainable clock frequency and compromised static timing analysis.
Innovation Solution
A method and apparatus that dynamically adjusts the control inputs to programmable delay elements across voltage islands, using a system controller with multiplexers to optimize clock tree balancing for different operational modes, reducing clock skew and enabling higher operating frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If voltage islands are used to reduce power consumption, then power savings are achieved, but clock distribution balancing becomes more complex
Solution Approach 1:
The patent implements dynamic voltage scaling that allows voltage islands to change their operating voltage levels based on performance requirements. This dynamic adjustment capability enables the clock distribution network to adapt to different voltage conditions, resolving the complexity issue by making the system flexible rather than static. The clock tree can be re-balanced dynamically when voltage changes occur.
Solution Approach 2:
The patent changes the voltage parameter of voltage islands dynamically to meet performance targets. By allowing voltage to vary between different operating points rather than being fixed, the system can optimize power consumption while maintaining clock distribution integrity through appropriate voltage selection and clock tree adjustment.
2Device complexity
If static voltage islands are used with predetermined voltage settings, then design simplicity is maintained, but timing penalties and voltage skew increase
Solution Approach 1:
The patent transitions from static to dynamic voltage scaling, allowing voltage islands to adjust their voltage levels based on current performance requirements. This dynamic capability enables the system to optimize timing by selecting appropriate voltage levels, reducing timing penalties and voltage skew while maintaining manageable design complexity through systematic control mechanisms.
3Adaptability or versatility
If dynamic voltage scaling is implemented, then power and performance optimization is achieved, but clock tree balancing becomes more difficult
Solution Approach 1:
The patent implements dynamic voltage scaling with corresponding dynamic clock tree balancing. When voltage islands change their voltage levels, the clock distribution network dynamically adjusts to maintain proper timing. This is achieved through mechanisms that detect voltage changes and automatically rebalance the clock tree, making the complexity manageable while retaining the benefits of power and performance optimization.
Solution Approach 2:
The system employs feedback mechanisms where voltage changes in voltage islands are detected and used to trigger appropriate clock tree balancing adjustments. This feedback loop ensures that the clock distribution network remains synchronized with the current voltage states, automatically resolving timing issues without requiring complex manual intervention.
4Adaptability or versatility
If voltage islands operate at multiple operating points, then performance flexibility is improved, but clock skew and timing penalties worsen
Solution Approach 1:
The patent enables voltage islands to operate at multiple voltage levels for performance flexibility while implementing dynamic clock tree balancing that adapts to the current voltage configuration. This dynamic adjustment ensures that clock timing precision is maintained even as voltage levels change, by automatically compensating for the timing differences introduced by voltage variations.
Data Source
AI summary
A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.