ASIC Core Partitioning Across Singulatable Die Gaps
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Solution Overview
Problem
Existing ASIC implementations with multiple identical die in a multi-chip-module suffer from increased power consumption due to die-to-die I/O interfaces, while single monolithic dies consume more power when the total quantity of instantiated functions is reduced.
Innovation Solution
The design of a semiconductor wafer with processing cores connected via standard routing over a gap, allowing for scalable partitioning and singulation into single or grouped cores, reducing the need for high-power die-to-die I/O interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple identical die are connected in a multi-chip-module, then the total quantity of instantiated functions can be scaled, but power consumption increases due to die-to-die I/O interfaces
Solution Approach 1:
The patent merges multiple processing cores onto a single monolithic die, eliminating the need for die-to-die I/O interfaces. This consolidation allows multiple functions to be instantiated on one chip while avoiding the power overhead of inter-die communication, thus resolving the contradiction between scaling function quantity and reducing power consumption.
Solution Approach 2:
The patent segments the monolithic die into multiple independent processing cores that can be individually activated or deactivated. This segmentation allows the system to scale the quantity of instantiated functions by enabling only the required cores, thereby maintaining low power consumption while providing scalability.
2Use of energy by moving object
If a single monolithic die is used with multiple instantiations of functions, then power consumption is reduced compared to multi-chip-module, but power consumption increases when the total quantity of instantiated functions is reduced
Solution Approach 1:
The patent implements dynamic power management capabilities that allow the system to selectively activate or deactivate processing cores based on the required functionality. This dynamic control enables the system to adapt power consumption to the actual quantity of instantiated functions, resolving the contradiction between low power consumption and flexibility in function scaling.
Solution Approach 2:
The patent changes the operational parameters of the monolithic die by allowing selective activation of processing cores. This parameter change enables the system to optimize power consumption according to the number of functions being instantiated, providing both low power consumption and adaptability in function scaling.
3Adaptability or versatility
If processing cores are spaced apart by a target distance for separating die structures, then flexible die configurations and singulation are enabled, but device complexity increases
Solution Approach 1:
The patent implements universal routing infrastructure that can handle multiple configuration scenarios. The same routing fabric and I/O interfaces support both monolithic operation and separated die configurations, eliminating the need for separate routing designs and reducing overall device complexity while maintaining flexibility.
Solution Approach 2:
The patent provides excessive routing capacity and I/O interfaces that can be fully utilized in monolithic configurations or partially used when die are separated. This partial action approach allows the system to maintain simple routing logic while providing the flexibility to configure die in various arrangements without increasing complexity.
Data Source
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AI summary
A semiconductor wafer is provided including: processing cores; and die structures each including at least one processing core. Each processing core includes a set of first input output (I/O) interfaces configured for communication between the processing core and a second processing core, wherein the processing core and the second processing core are included in a first die structure of the die structures. Each processing core includes a second input output (I/O) interface configured for communication between the processing core and a third processing core, wherein the third processing core is included in a second die structure of the die structures. The processing cores are spaced apart by a target distance associated with separating one or more processing cores or one or more die structures from the semiconductor wafer.