ASIC Runtime Reconfiguration Through Criticality-Based Power Gating
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Solution Overview
Problem
Current methods for identifying functionally critical logic in ASICs for power reduction are inefficient, especially in larger designs, due to high simulation penalties and increased area overhead, and fail to achieve energy-quality trade-offs without voltage scaling.
Innovation Solution
A method that classifies logic into regions based on functional criticality, power gates each region at runtime, and optimizes adder-multiplier combinations and flip flops to achieve a target error threshold without voltage over scaling, using peak-signal-to-noise-ratio (PSNR) as an error metric and incremental bit analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate-level simulations are performed to identify functionally critical logic, then accuracy of identification is improved, but simulation time increases significantly
Solution Approach 1:
The design is segmented into functionally critical and non-critical regions based on error resilience characteristics. By dividing the ASIC into these segments, the patent enables selective analysis and power gating strategies without requiring exhaustive gate-level simulation of the entire design, thus reducing simulation time while maintaining identification accuracy.
Solution Approach 2:
The patent performs preliminary classification of logic elements into criticality bins before detailed analysis. This preliminary action identifies candidate regions for power gating based on simpler metrics, allowing the system to focus computational resources on verifying only the most promising candidates, thereby reducing overall simulation time.
2Use of energy by moving object
If voltage scaling is used to reduce power consumption, then energy savings are achieved, but area overhead increases due to routing multiple voltage planes and level shifters
Solution Approach 1:
The patent extracts and removes the need for complex voltage scaling infrastructure by using power gating instead. By taking out the level shifters and multiple voltage plane routing, the system achieves power reduction without the associated area overhead, while still enabling energy-quality trade-offs through selective gating of non-critical logic regions.
Solution Approach 2:
The patent employs simple power switches as disposable, low-cost elements to gate power to non-critical regions. These power switches are much simpler and occupy far less area than level shifters, providing an economical solution for power reduction that avoids the area penalties of traditional voltage scaling approaches.
3Use of energy by moving object
If power gating is applied to reduce power consumption, then energy savings are achieved, but error threshold may be exceeded in critical logic regions
Solution Approach 1:
The patent applies power gating selectively to specific non-critical logic regions while leaving critical regions unaffected. By making the power gating local rather than global, the system achieves energy savings in non-essential areas without compromising the reliability or error threshold of critical functionality, thus resolving the contradiction between power reduction and error tolerance.
4Speed
If manual restructuring is performed to optimize significant computations, then computation speed is improved, but design complexity increases and generalizability decreases
Solution Approach 1:
The patent develops a universal framework for identifying functionally critical logic and applying power gating that can be generalized across different ASIC designs. Rather than manual restructuring specific to each design, the framework provides automated, design-agnostic methodology that maintains computation speed through selective power gating while avoiding the increased design complexity and loss of generalizability associated with manual optimization.
Data Source
AI summary
Methods for reconfiguring an ASIC at runtime without using voltage over scaling. A functional criticality of a set of logic in the ASIC is identified. Then, the set of logic are classified into a set of regions based on the functional criticality, each region of the set of regions having a target error threshold. Further, each region is power gated at runtime based on the functional criticality such that the target error threshold is achieved without using voltage over scaling.