On-ASIC ECC Beat Encoding for High-Rate Memory Reliability
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Solution Overview
Problem
Current error correction code (ECC) techniques for memory devices, such as on-die and link ECCs, increase the cost and complexity of DRAM components and introduce latency issues due to high-speed protocols like Compute Express Link, necessitating a more efficient method for error detection and correction without compromising data rates.
Innovation Solution
Implementing on-ASIC ECC encoding and decoding on beats of data, where a digital system assembles words of varying lengths, constructs a parity word, and adds it to form a beat, enabling error correction without the need for on-die or link ECCs, thereby reducing costs and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die or link ECCs are implemented, then error detection and correction capability is improved, but cost and device complexity increase
Solution Approach 1:
The patent extracts the ECC encoding function from the memory device itself and relocates it to the memory controller (ASIC). The memory controller now performs the error correction encoding on data beats before transmission, eliminating the need for complex on-die ECC circuits in the DRAM components. This extraction reduces device complexity and cost at the memory device level while maintaining error correction capability at the system level.
2Reliability
If traditional ECC algorithms are executed on memory words, then error correction is achieved, but latency increases and data rates are reduced
Solution Approach 1:
The patent segments the error correction encoding process to operate on data beats (groups of multiple words) rather than processing each word individually. By assembling multiple words into a beat and performing a single ECC encoding operation on the entire beat, the system reduces the frequency of encoding operations and minimizes latency, thereby maintaining high data rates while ensuring error correction capability.
Solution Approach 2:
The patent enables continuous data transmission by performing ECC encoding on complete data beats without interrupting the data flow. The encoding process is integrated into the memory controller's data path, allowing uninterrupted processing of data beats and maintaining the high-speed protocol requirements while providing error correction.
Data Source
AI summary
There are provided methods and systems for on-ASIC error control coding for verifying the integrity of data from a memory. For example, there is provided a method for encoding data into a beat. The method can be executed by a digital system configured to receive the data and construct the beat. The method includes assembling, by the digital system, a plurality of words consecutively. The plurality of words can include a first set of words in which each word has a length W, where W is the beat width. The plurality of words can further include a second set of words in which each word has a length that is smaller or equal to W. The method can further include constructing a parity word of length W, wherein each bit in the parity word is a parity associated with a distinct word in the first and second set of words. The method further includes adding the parity word to the plurality of words to form the beat.