On-ASIC ECC Encoding for High-Rate Memory Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in detecting and correcting errors without compromising data rates, particularly in high-speed protocols like Compute Express Link, due to the use of on-die and link ECCs that increase costs and reliability burdens.
Innovation Solution
Implementing on-ASIC ECC encoding and decoding on beats of data, using a parity check matrix to construct codewords with embedded parity words, allowing error detection and correction without the need for on-die and link ECCs, thereby reducing costs and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die and link ECCs are used for error detection and correction, then reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the ECC functionality from the traditional on-die and link infrastructure and relocates it to the ASIC level. Specifically, the encoder and decoder circuits are integrated into the ASIC, while the memory array itself remains unchanged. This extraction allows error correction capabilities to be maintained while simplifying the overall system architecture by removing separate on-die ECC logic and link-level ECC mechanisms.
Solution Approach 2:
The ASIC integrates multiple functions including data encoding, decoding, error correction, and memory control into a single universal component. The encoder generates parity bits for error detection, the decoder performs syndrome calculation and error correction, and the entire system operates with standard memory interfaces. This multi-functionality consolidates what would traditionally require separate on-die ECC circuits, link ECC mechanisms, and control logic into one unified ASIC.
2Reliability
If traditional ECC scanning and correction procedures are executed, then error correction is achieved, but data rate is reduced due to latency
Solution Approach 1:
The encoder performs preliminary encoding of data into codewords with embedded parity bits before data is written to memory. This preliminary action ensures that error correction capability is built into the data structure in advance, eliminating the need for complex post-read scanning and correction procedures. The decoder then performs rapid syndrome calculation and correction on the fly during normal read operations, maintaining high data rates while ensuring error correction.
3Reliability
If on-die peripheral systems scan memory array and execute ECC algorithms, then errors are detected and fixed, but latency increases
Solution Approach 1:
The patent replaces the mechanical scanning process with an electronic syndrome calculation mechanism. Instead of physically scanning memory sections and executing correction algorithms sequentially, the decoder uses parallel bitwise operations to calculate syndromes and identify errors in a single pass through the data. This substitution of mechanical scanning with electronic computation dramatically reduces the time required for error detection and correction.
Data Source
AI summary
Provided are methods and systems for decoding a beat of data. There is provided a system for decoding a beat of data that comprises a first module configured to generate a syndrome vector from the beat of data and from a parity check matrix by computing syndrome components based on the parity check matrix and the beat of data, and a second module configured to accumulate contributions of the beat of data into a register based on the syndrome components to create the syndrome vector. The received data is encoded to form a payload including parity data, and the parity data is stored at an end of the payload, the payload being arranged in the memory transfer block which includes a code word for error detection.