Timing-Driven Hardware Emulation for ASIC Verification
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Solution Overview
Problem
Conventional methods for verifying ASIC designs are time-consuming and lack flexibility, particularly in catching timing-related issues, as they often rely on gate-level simulation that is not implemented on actual hardware.
Innovation Solution
Circuit design tools that account for timing constraints during hardware emulation, generating variable-frequency timing constraints and converting point-to-point interconnect delays to port-to-port delays to simplify the emulation process, allowing for faster and more accurate functional testing on programmable integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-level simulation is used for ASIC design verification, then functional testing can be performed, but timing-related issues cannot be caught and the process is time-consuming
Solution Approach 1:
The patent segments the ASIC design into multiple partitioned blocks that can be independently emulated on separate programmable logic devices. This segmentation enables parallel verification of different design portions, significantly reducing the overall verification time while maintaining timing accuracy through hardware-based emulation of each partition
Solution Approach 2:
The patent introduces an intermediary system that includes a partitioning module, constraint generation module, and emulation controller. This intermediary hardware/software system acts as a bridge between the ASIC design and the programmable logic devices, enabling accurate timing verification through hardware emulation while coordinating the complex verification process
2Reliability
If hardware emulation is used for ASIC verification, then timing issues can be caught, but the process is complex and requires multiple programmable devices
Solution Approach 1:
The patent divides the ASIC design into partitioned blocks that can be independently loaded onto separate programmable logic devices. Each partition is emulated independently with its own configuration data, allowing timing verification without requiring a single complex emulation system. This segmentation simplifies the overall emulation architecture while maintaining timing accuracy
Solution Approach 2:
The patent creates a universal emulation approach where standard programmable logic devices are used to emulate different partitions of the ASIC design. The same type of programmable device can verify multiple different partitions, reducing the need for specialized expensive emulation hardware and simplifying the system architecture
3Productivity
If conventional emulation methods are used, then functional testing can be performed, but timing constraints are not considered and timing bugs are missed
Solution Approach 1:
The patent performs preliminary extraction of timing constraints from the ASIC design before the emulation process. These timing constraints are incorporated into the configuration data that programs the programmable logic devices. This preliminary action ensures that timing verification is built into the emulation process from the start, allowing both functional testing and timing verification to occur simultaneously without compromising either
Data Source
AI summary
Programmable integrated circuits may be used to perform hardware emulation of an application-specific integrated circuit (ASIC) design. The ASIC design may be loaded onto the programmable integrated circuit. During hardware emulation operations, an emulation host may be used to coordinate testing of the DUT on the programmable device. Circuit design tools may be used to extract parasitics from the ASIC design, compute low-level interconnect delays, convert the interconnect delays to higher-level port-to-port delays, convert the port-to-port delays to timing constraints, and generate corresponding configuration data for programming the programmable integrated circuit to emulate the ASIC design. The programmable integrated circuit may then be tested for functional and performance integrity.