Centralized Error Handling in ASICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern application specific integrated circuits (ASICs) face complexity and latency issues due to existing error handling schemes, which lead to 'back pressure' among hardware blocks and increased verification complexity, delaying time to market.
Innovation Solution
A centralized error handling system using an error queue manager and error state manager to isolate and clear errors, allowing hardware blocks to ignore requests associated with errored commands and release resources, thereby preventing back pressure and simplifying the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware blocks halt operation upon experiencing an error, then the error is contained and does not propagate, but other hardware blocks experience back pressure and latency spikes
Solution Approach 1:
The system segments error handling by introducing an error queue that separates error reporting from error processing. Hardware blocks can independently report errors to the queue manager and continue processing other commands, while the queue manager systematically manages error states without blocking other operations.
Solution Approach 2:
The error queue manager acts as an intermediary between hardware blocks and the firmware. It receives error reports from hardware blocks, manages error states in the error queue, and coordinates with firmware to clear errors, preventing direct halting of hardware blocks and eliminating back pressure on other commands.
2Reliability
If multiple hardware blocks are placed in error state simultaneously, then all errors are tracked, but system complexity increases significantly
Solution Approach 1:
The system merges multiple error states into a single centralized error queue managed by the queue manager. Instead of each hardware block independently managing its error state, all error states are consolidated in one location, simplifying the overall system architecture while maintaining the ability to track multiple simultaneous errors.
Solution Approach 2:
The error queue manager serves multiple functions: it receives error reports from any hardware block, tracks error states for multiple commands, coordinates with firmware for error clearing, and prevents back pressure. This universal error handling mechanism replaces complex individual error management in each hardware block.
3Reliability
If error handling schemes are designed to deal with multi-error corner cases, then all error scenarios are covered, but verification complexity and time to market increase
Solution Approach 1:
The system performs preliminary error state management by maintaining an error queue that proactively tracks error states before they propagate. The queue manager is pre-configured to handle multiple error scenarios, reducing the need for extensive verification of complex error handling logic during manufacturing.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
In one embodiment, a system comprises a plurality of hardware blocks, each of the plurality of hardware blocks configured to perform a function in response to a request associated with a command, an error queue manager configured to receive an error message from at least one of the plurality of hardware blocks and store the error message in an error queue, the error message including a command identifier of a command in error, and an error state manager including an error state bitmap, the error state bitmap storing an error state bit for each of a plurality of command identifiers, the error state bit indicating either command in error or command not in error; the error state manager configured to set the error state bit for the command identifier of the command in error to indicate command in error in response to an error state message, the error state message including the command identifier of the command in error.