ASIC Error Simulation via Data Masking and Interrupt Injection
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Solution Overview
Problem
Current methods for simulating errors in complex systems are costly, cumbersome, and often require significant additional hardware or software, which can slow system performance and complicate ASIC design, making it difficult to thoroughly test and validate system responses to various errors.
Innovation Solution
A flexible mechanism is introduced that allows for error simulation by modifying data and interrupt behavior at the processor interface, using ASIC logic to simulate errors without intrusive test circuitry, allowing for extensive range of firmware and software code paths to be exercised without impacting the ASIC design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If test circuitry is inserted into the hardware to simulate errors, then error simulation capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the error simulation functionality from the hardware circuitry and relocates it to the software/firmware level. Instead of embedding test circuitry within the ASIC, the solution uses software-based error injection mechanisms that interact with the ASIC through its normal interfaces, thereby eliminating the need for additional hardware test circuitry while maintaining comprehensive error simulation capability
Solution Approach 2:
The patent introduces an intermediary software layer that acts as a mediator between the test environment and the ASIC. This software intermediary can generate and inject various error conditions into the system without requiring direct hardware modification, thus maintaining ASIC design simplicity while enabling extensive error simulation scenarios
2Adaptability or versatility
If additional hardware test equipment is used to simulate errors, then error simulation capability is improved, but cost and device complexity increase
Solution Approach 1:
The patent creates a virtual copy of error simulation functionality through software rather than requiring physical hardware test equipment. The software can replicate various error conditions that would traditionally require expensive specialized hardware, providing the same simulation capability at minimal cost
Solution Approach 2:
The system performs self-testing and error simulation through integrated software mechanisms rather than requiring external test equipment. The ASIC and surrounding software can generate, detect, and respond to error conditions autonomously, eliminating the need for separate expensive test hardware
3Adaptability or versatility
If firmware interception and modification is used to simulate errors, then error simulation capability is improved, but system performance decreases
Solution Approach 1:
The patent applies error simulation selectively rather than continuously. The software-based error injection is activated only when and where needed for specific test scenarios, rather than constantly monitoring and modifying all firmware operations. This partial application of error simulation maintains system performance while providing comprehensive testing capability
Data Source
AI summary
Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.