Centralized Error Handling in ASICs for Latency Reduction
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Solution Overview
Problem
Modern application specific integrated circuits (ASICs) face complexity and latency issues due to existing error handling schemes, which cause back pressure in the system and delay the time to market, especially in multi-error corner cases where multiple hardware blocks are in an error state.
Innovation Solution
A method and system for centralized error handling that involves identifying queues subject to a reset, halting command fetching, updating an error state bitmap, and releasing resources associated with errored commands, allowing for efficient error management and resource reallocation without interfering with other commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware blocks halt operation when experiencing an error, then error handling reliability is improved, but system latency increases due to back pressure on other hardware blocks
Solution Approach 1:
The patent segments the error handling process by introducing a dedicated error handling hardware block that operates independently from functional hardware blocks. This segmentation allows error processing to occur in parallel without blocking command execution in other blocks, thereby maintaining reliability while reducing latency caused by back pressure.
Solution Approach 2:
The patent introduces an intermediary error handling block that receives error notifications from functional hardware blocks and processes them separately. This intermediary structure prevents direct blocking between error-prone functional blocks and the error handling logic, allowing commands to continue flowing through the system while errors are processed in the background.
2Reliability
If multiple hardware blocks are placed in error state simultaneously, then comprehensive error coverage is improved, but device complexity increases due to multi-error corner case handling
Solution Approach 1:
The patent merges all error handling functionality into a single centralized error handling block that consolidates error state management for multiple hardware blocks. This merging approach maintains comprehensive error coverage while reducing device complexity by eliminating the need for each hardware block to have its own error handling logic and by providing a unified interface for error processing.
3Reliability
If a full system reset is performed to clear errors, then error state clearing is improved, but productivity decreases due to abortion of all active commands
Solution Approach 1:
The patent applies local quality by enabling selective clearing of error states in the centralized error handling block rather than requiring a full system reset. This allows individual error states to be cleared independently based on specific conditions, maintaining reliability by ensuring proper error clearance while preserving productivity by allowing non-errored commands to continue executing without interruption.
Data Source
AI summary
In one embodiment, a method for reset and error handling comprises identifying at least one queue of a plurality of queues that is subject to a reset, halting fetching of commands from a host that are associated with the at least one queue subject to the reset, halting reallocation of command identifiers of completed commands to commands received from the host that are associated with the plurality of queues, identifying at least one command identifier associated with the at least one queue subject to the reset, updating an error state bitmap to indicate the at least one command identifier as a command in error, resuming reallocation of command identifiers of completed commands after updating the error state bitmap, and resuming fetching of commands from the host that are associated with the at least one queue subject to the reset after resuming reallocation of command identifiers of completed commands.