Embedded Fault Injection Logic for ASIC Diagnostic Verification
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Solution Overview
Problem
Conventional methods for testing diagnostic software on ASICs are challenging due to limited accessibility and the difficulty in simulating intermittent failures within embedded systems, making it hard to verify the operation of diagnostic processes.
Innovation Solution
The implementation of embedded fault injection logic within ASICs allows for programmable control of fault injection, enabling the simulation of multiple error types across various locations, facilitating the testing of diagnostic software without external probes and allowing real-time programmability to specify fault type, duration, and location.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external probes are used to inject faults into ASIC data lines, then fault injection capability is achieved, but physical accessibility and ease of operation deteriorate due to limited access to embedded circuits
Solution Approach 1:
The fault injection logic is nested directly within the ASIC chip structure, with injection circuits integrated at multiple hierarchical levels (data line level, module level, and chip level). This nested architecture allows fault injection capabilities to be embedded deep within the device without requiring external physical access to internal data lines.
Solution Approach 2:
Test access mechanisms (TAMs) and embedded test interfaces serve as intermediaries between external test equipment and internal ASIC data lines. These intermediary structures provide controlled access points that enable fault injection without requiring direct physical probing of embedded circuits, thus improving ease of operation while maintaining reliability.
2Reliability
If conventional hardware simulation is used to test ASICs, then hardware operation can be verified, but the ability to test diagnostic processes deteriorates
Solution Approach 1:
The embedded fault injection logic is designed with multi-functionality, serving both hardware verification and diagnostic process testing through a single integrated system. The same injection circuits and control mechanisms can induce faults for hardware testing while simultaneously enabling diagnostic software to detect and respond to those faults, thus achieving both objectives without separate testing infrastructure.
Solution Approach 2:
The system incorporates feedback mechanisms where diagnostic processes monitor the effects of injected faults and report back on system response. This feedback loop enables verification that diagnostic software correctly detects, logs, and responds to faults, providing adaptability for diagnostic process testing while maintaining hardware verification capabilities.
3Ease of manufacture
If simple fault injection is implemented, then ease of manufacture is improved, but testing comprehensiveness deteriorates
Solution Approach 1:
The fault injection system is segmented into modular components distributed throughout the ASIC architecture, with independent injection points at multiple locations and levels. Each segment can be manufactured and tested independently using simple procedures, yet the collective system provides comprehensive fault coverage across the entire device, reconciling manufacturing simplicity with testing thoroughness.
Data Source
AI summary
Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.