ASIC Fast Reroute via ECMP Table Mapping
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Solution Overview
Problem
Current Fast Reroute (FRR) methods in the driver layer fail to meet the required switching time due to the need for frequent route deletions and additions, especially when dealing with a large number of invalid Label Switched Paths (LSPs), which is not efficiently supported by Application Specific Integrated Circuit (ASIC) chips.
Innovation Solution
Implement FRR by utilizing the Equal-Cost Multi-Path (ECMP) table on ASIC chips, where the upper layer protocol software manages and configures FRR routes, writes the active next hop IP address into the ECMP table, and creates a software table to store correspondence between FRR and ECMP groups, allowing for efficient switching by updating the next hop without deleting or adding subnet routes multiple times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the driver deletes and adds routes multiple times to implement FRR switching, then the FRR protection function is achieved, but the switching time exceeds the 50ms requirement
Solution Approach 1:
The patent pre-establishes backup LSP routes and configures them in the ECMP table before failure occurs. When a link or node failure happens, the system immediately switches to the pre-configured backup route without needing to delete and add routes dynamically, thus achieving fast switching within 50ms while maintaining FRR protection functionality
Solution Approach 2:
The patent reuses the existing ECMP (Equal-Cost Multi-Path) routing mechanism and hardware table structures for FRR implementation. By making the ECMP table serve dual purposes (both for load balancing and for FRR backup routing), the system achieves fast switching without requiring separate FRR hardware tables or modifying ASIC chip functions, thereby reducing switching time while maintaining protection capability
2Reliability
If the driver manages FRR routes through multiple delete and add operations, then route protection is achieved, but the system complexity and processing overhead increase
Solution Approach 1:
The patent makes the ECMP table and its management mechanisms serve multiple functions: both for traditional load balancing routing and for FRR backup routing. This eliminates the need for separate FRR route management logic in the driver, reducing processing complexity while maintaining route protection through the unified ECMP framework
Solution Approach 2:
The patent combines FRR backup route management with the existing ECMP routing management in the driver. By merging these functions and using a unified approach to manage both primary and backup routes through the ECMP table, the system reduces driver processing complexity and the number of operations required while maintaining reliable route protection
3Speed
If NP chips are used to implement FRR with hardware table entries, then switching speed is improved, but device cost increases
Solution Approach 1:
The patent enables standard ASIC chips to perform FRR switching by reusing their existing ECMP table structures and management interfaces. This allows ASIC chips to provide NP-chip-level FRR switching speed without requiring expensive NP chip hardware, achieving fast switching while maintaining cost-effectiveness through multi-functional use of existing chip capabilities
Solution Approach 2:
The patent creates a software-level representation of FRR routing that mirrors the functionality of hardware-based FRR in NP chips. By copying the essential FRR switching logic and table structures into the driver layer and mapping them to ECMP table operations, the system achieves similar switching performance on cheaper ASIC chips without requiring actual NP chip hardware
Data Source
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AI summary
The present invention discloses a method for implementing Fast Reroute (FRR). The method comprises the following steps of: a system starting up an upper layer protocol to manage and configure a FRR route; an upper layer sending down a active next hop of the FRR; a driver writing an IP address of the FRR into an ECMP table and creating a software table to record correspondence between a FRR group and ECMP group; informing the driver of a prefix address of a subnet route and the index of the FRR group, and the driver finding the index of the ECMP group in the software table, and writing information of the subnet route and the index of the ECMP group into hardware; an upper layer informing the driver of the index of the FRR and an IP address of a new standby next hop when the IP address of the active next hop of the FRR group fails; the driver looking up the software table for the index of the ECMP group, and updating the next hop address of the ECMP group to the new IP address. The present invention improves the response speed of the system designed using chips for FRR switch.