ASIC Hardening From Software Execution for Faster Verification
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Solution Overview
Problem
The existing methods for converting high-level programming languages into ASIC designs face challenges such as implementation gaps, inefficient logic creation, and verification difficulties due to the lack of clocking information, leading to time-consuming and error-prone manual conversion processes, and suboptimal performance in hardware prototypes.
Innovation Solution
A system and method that involves analyzing and partitioning software programs executed on a processing system capable of parallel processing, generating hardware descriptions, and 'hardening' specific portions to create an ASIC, allowing for real-time testing and optimization for performance, area, and power consumption, with the ability to scale resources and integrate IP blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If manual conversion from high-level language to HDL is performed, then functional accuracy can be maintained, but development time and complexity increase significantly
Solution Approach 1:
The patent introduces an intermediary processing system that executes the high-level language program and generates corresponding HDL code. This intermediary automatically translates C/C++ code into Verilog/VHDL while preserving functional accuracy, eliminating the need for manual conversion and significantly reducing development time.
Solution Approach 2:
The patent replaces the manual mechanical process of converting high-level language to HDL with an automated computer-based system. The processing system automatically analyzes the high-level program, generates equivalent HDL code, and synthesizes it into gate-level logic, substituting human effort with automated computational processes.
2Loss of time
If automatic behavioral synthesis is used to convert high-level programs to HDL, then development time is reduced, but logic efficiency deteriorates
Solution Approach 1:
The patent performs preliminary analysis of the high-level language program execution on a processing system to understand the actual computational requirements and timing characteristics. This preliminary action enables the generated HDL code to be optimized for logic efficiency while maintaining automated conversion benefits, avoiding the inefficiencies of traditional behavioral synthesis.
3Reliability
If FPGAs are used for prototyping, then design verification is enabled, but system speed and performance are reduced
Solution Approach 1:
The patent inverts the traditional prototyping approach by first implementing the design in high-level language, executing it on a processing system to verify functionality at full speed, and then automatically generating HDL code for ASIC implementation. This reversal allows verification at desired speed before committing to final ASIC design, rather than accepting FPGA speed limitations.
4Reliability
If multiple development cycles are used to transform high-level model to ASIC, then functional correctness can be verified, but time and resource consumption increase
Solution Approach 1:
The patent merges multiple development cycles into a single integrated process. The processing system simultaneously executes the high-level program for verification and generates the corresponding HDL code for ASIC implementation in one unified workflow, eliminating the need for separate verification and implementation cycles.
Solution Approach 2:
The patent implements feedback by executing the high-level language program on the processing system to verify functional correctness, using the execution results to guide and validate the automatic HDL code generation process. This feedback mechanism ensures functional correctness while maintaining high development efficiency through automated iteration.
Data Source
AI summary
System and method for developing an ASIC. A software program may be stored which includes program instructions which implement a function. The software program may be executed on a processing system at a desired system speed and may be validated based on the execution. A first hardware description of at least a portion of the processing system may be stored and may specify implementation of at least a portion of the processing system. A second hardware description may be generated that corresponds to a first portion of the first hardware description. The second hardware description may specify a dedicated hardware implementation of a first portion of the software program executing on the processing system. Generation of the second hardware description may be performed one or more times to fully specify the ASIC. An ASIC may be created which implements the function of the software program.