On-Chip Security Circuitry for ASIC Hardware Trojan Detection
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Solution Overview
Problem
Integrated circuits (ICs) fabricated in untrusted foreign foundries are vulnerable to hardware Trojan horse (HTH) threats, making it difficult to detect and mitigate malicious modifications that can compromise security and performance, especially due to the complexity and size of ASICs, which creates risks across various industries including government and commercial sectors.
Innovation Solution
The Application Specific Integrated Circuit (ASIC) Redesign for Security and Analysis (ASRA) testing tool incorporates on-chip security circuitry and design-for-test (DFT) codes to detect and mitigate HTHs by identifying untrusted modules, generating testing circuits, and simulating their operation to ensure validity, thereby providing enhanced security measures and reducing detection costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If ASIC size and complexity are increased to improve capabilities and efficiency, then processing power and functionality are enhanced, but vulnerability to HTH insertion and detection difficulty increase
Solution Approach 1:
The patent segments the ASIC design into multiple modules and inserts independent testing circuits for each module. This segmentation allows the large complex ASIC to be divided into smaller, more manageable units that can be tested individually, making HTH detection feasible despite the overall system complexity.
Solution Approach 2:
The patent introduces testing circuits as intermediary components between the ASIC modules and the external environment. These testing circuits act as mediators that monitor and detect HTH activity without interfering with the normal operation of the main ASIC, enabling detection in complex systems.
2Ease of manufacture
If conventional testing methods are used to reduce cost, then fabrication cost is lowered, but HTH detection capability is insufficient
Solution Approach 1:
The patent incorporates testing circuits during the design and fabrication process itself, rather than adding them afterward. This preliminary action ensures that detection capability is built into the ASIC from the start, providing reliable HTH detection without requiring expensive post-fabrication modifications or specialized testing equipment.
Solution Approach 2:
The testing circuits are designed to autonomously monitor and detect HTH activity within the ASIC modules without requiring external intervention or complex testing equipment. This self-service capability enables reliable detection while keeping the system simple and cost-effective.
3Object-affected harmful factors
If HTH triggers are made more隐蔽 (hidden) to improve malicious capability, then detection becomes nearly impossible, but security risk increases
Solution Approach 1:
The testing circuits continuously monitor module activity and provide feedback about unusual patterns that may indicate HTH triggering. This feedback mechanism enables the detection of even highly隐蔽 triggers by analyzing deviations from normal operational patterns, maintaining security against sophisticated threats.
Solution Approach 2:
The patent replaces traditional physical inspection methods with electronic monitoring through testing circuits. This substitution enables the detection of subtle HTH triggers that would be impossible to detect through conventional means, effectively countering increasingly sophisticated malicious capabilities.
Data Source
AI summary
Disclosed herein is application specific integrated circuit (ASIC) redesign for security and analysis testing tool, which includes hardware description language code with on-chip security circuitry for detecting and mitigating hardware Trojan horses (HTHs) in an ASIC chip. The testing tool is used between a design stage of the ASIC chip and a synthesis phase of production of the ASIC chip to add test circuitry to the ASIC chip in order to facilitate testing and protecting of the ASIC chip from the HTHs long after production. The test circuitry facilitates search for HTHs, HTH triggering events, and changes made to the ASIC if the HTH has been activated.