Switching ASIC Heartbeat Packet Processing
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Solution Overview
Problem
In network systems, the full-stack processing of heartbeat packets by the CPU leads to substantial time and resource consumption, causing issues such as timing requirements not being met, false indications of links being down, and network traffic delays or loss.
Innovation Solution
The use of a switching ASIC to process heartbeat packets, leveraging its aging mechanism to determine the state of communication links, reduces the load on the CPU and enables faster processing of heartbeat packets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU performs full-stack processing of heartbeat packets, then the processing is thorough and accurate, but the processing time and resource consumption increase substantially
Solution Approach 1:
The patent segments the heartbeat packet processing function from the CPU by implementing a dedicated hardware module that handles only the essential heartbeat processing tasks. This separation allows the CPU to focus on higher-level processing while the hardware module handles time-critical heartbeat operations, thereby reducing CPU processing time and resource consumption while maintaining processing accuracy.
Solution Approach 2:
The patent introduces a hardware intermediary module between the network interface and the CPU that专门 handles heartbeat packet processing. This intermediary performs the time-sensitive tasks of receiving, validating, and processing heartbeat packets using hardware accelerators, thus mediating between the network layer and CPU to eliminate the bottleneck of full-stack CPU processing.
2Measurement precision
If the CPU processes heartbeat packets at high rate, then the link state detection is frequent and accurate, but the CPU capacity is exceeded causing timing requirements not to be met
Solution Approach 1:
The patent extracts the heartbeat packet processing function from the CPU by implementing a dedicated hardware module that handles only the essential heartbeat processing tasks. This extraction allows the CPU to focus on higher-level processing while the hardware module handles time-critical heartbeat operations, thereby reducing CPU processing time and resource consumption while maintaining processing accuracy.
Solution Approach 2:
The patent replaces the CPU's software-based full-stack processing with a hardware-based processing mechanism. The hardware module uses dedicated circuitry and hardware accelerators to process heartbeat packets at line rate, substituting the mechanical/CPU-based processing with an optimized hardware system that can handle high volumes of packets without exceeding CPU capacity.
3Reliability
If the CPU performs full-stack processing, then the processing is comprehensive, but false indications of links being down occur due to timing requirements not being met
Solution Approach 1:
The patent implements preliminary hardware-based processing of heartbeat packets before they reach the CPU. The hardware module performs initial validation, timing checks, and state determination in advance, ensuring that accurate link state information is prepared before CPU processing. This preliminary action prevents false indications by catching timing issues early in the processing pipeline.
Solution Approach 2:
The patent implements a feedback mechanism where the hardware module continuously monitors heartbeat packet reception and link state, providing real-time feedback to the CPU. This feedback loop allows the system to correct potential false indications by cross-validating hardware observations with CPU processing, ensuring accurate link state detection while maintaining processing completeness.
Data Source
AI summary
Systems and methods for increasing the speed with which a network device can process “heartbeat” packets that are transmitted between the network device and its peers to verify that the communication links between them are active, or to detect when the communication links go down (i.e., are inactive). Received heartbeat packets are processed primarily by a switching application specific integrated circuit (ASIC) rather than a CPU of the network device. The switching ASIC identifies heartbeat sessions corresponding to received heartbeat packets and resets aging timers for these sessions if the timers have not already expired. The reduced processing and faster timing mechanism of the switching ASIC enables the network device to accommodate spikes in the received packet rate.