ASIC Image Data Compression Circuit for Storage Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing image forming apparatuses face inefficiencies in data processing and storage due to the accumulation and transmission of large image data sets, leading to increased storage usage and potential data transfer issues between scanners, control circuits, and plotters.
Innovation Solution
An application-specific integrated circuit (ASIC) is developed, incorporating a communication circuit, multi-level fixed-length compression and decompression circuits, and selection circuits to manage image data processing and transmission efficiently between scanners, control circuits, and plotters, optimizing data reduction and transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If image data is accumulated in storage medium without compression, then image quality is preserved, but storage usage increases
Solution Approach 1:
The patent applies lossless compression algorithms that change the parameter of data representation without altering the underlying image information. The compression circuit transforms raw image data into a more compact form while preserving all original data points, thereby reducing storage usage while maintaining complete image quality integrity.
2Productivity
If compressed image data is transmitted from scanner to control circuit, then data transfer efficiency is improved, but processing complexity increases
Solution Approach 1:
The compression operation is performed preliminarily at the scanner side before data transmission begins. This preliminary compression reduces the volume of data that needs to be transmitted through the communication circuit to the control circuit, thereby improving data transfer efficiency while the added processing complexity is confined to the initialization phase rather than ongoing operations.
3Reliability
If lossless compression is applied to multi-level image data, then image quality is maintained, but processing time increases
Solution Approach 1:
The patent replaces complex mechanical or software-based lossless compression processes with a dedicated hardware compression circuit implemented in the ASIC. This hardware implementation performs lossless compression operations in parallel at the circuit level, dramatically reducing processing time while maintaining complete image quality through lossless algorithms designed for multi-level image data.
Data Source
AI summary
An ASIC includes: a communication circuit that communicates with a control circuit; a multi-level, fixed-length compression circuit that performs fixed-length compression on scanner-generated image data to output multi-level, fixed-length compressed image data; a tone processing circuit that performs tone processing on the scanner-generated image data to output reduced-level image data; a first selection circuit that selects one of the multi-level, fixed-length compressed image data and the reduced-level image data, as first selected image data to be transmitted by the communication circuit to the control circuit; a multi-level, fixed-length decompression circuit that performs fixed-length decompression on image data received by the communication circuit from the control circuit, to output fixed-length decompressed image data; and a second selection circuit that selects one of the fixed-length decompressed image data and the image data received by the communication circuit, as second selected image data to be output to the plotter.